CN-121562524-B - RTL code simulation method and device, storage medium, computer program product, server and system

CN121562524BCN 121562524 BCN121562524 BCN 121562524BCN-121562524-B

Abstract

The RTL code simulation method comprises the steps of obtaining RTL codes to be simulated, responding to a simulation acceleration mode to be selected to be a period accurate simulation acceleration mode, decomposing the RTL codes into a plurality of sub-modules, respectively extracting features of each sub-module, configuring an FPGA according to the features of each sub-module to configure hardware resources on the FPGA into an initial processor array matched with the sub-modules, and mapping the RTL codes into instruction streams to be downloaded to the initial processor array for simulation, wherein the instruction streams are generated according to an instruction set used by the initial processor array. Therefore, the processor array can be reconstructed, free switching of multiple simulation modes is realized, and the simulation efficiency and simulation flexibility are improved.

Inventors

LU MEIJUN

Assignees

浙江亿方杭创科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260122

Claims (14)

1. A method for simulating an RTL code, comprising: acquiring an RTL code to be simulated; The method comprises the steps of responding to a simulation acceleration mode to be selected as a cycle accurate simulation acceleration mode, decomposing the RTL code into a plurality of sub-modules, and respectively extracting characteristics of each sub-module, wherein the step of decomposing the RTL code into the plurality of sub-modules comprises the step of decomposing the RTL code into the plurality of sub-modules according to functional boundaries and interfaces of the RTL code, wherein the characteristics comprise operator types, data bit widths, parallelism, memory access modes and control logic complexity; Configuring an FPGA according to the characteristics of each of the plurality of sub-modules so as to configure hardware resources on the FPGA into an initial processor array matched with the plurality of sub-modules; Mapping the RTL code into an instruction stream, and downloading the instruction stream onto the initial processor array for simulation, wherein the instruction stream is generated according to an instruction set used by the initial processor array; The configuration of the FPGA according to the characteristics of each of the plurality of sub-modules to configure hardware resources on the FPGA as an initial processor array matched with the plurality of sub-modules comprises the steps of calculating the matching degree between the plurality of sub-modules and each processor array template in a simulation special processor array library, wherein the simulation special processor array library stores a plurality of processor array templates which are used for configuring the hardware resources on the FPGA as corresponding processor cores, and configuring the hardware resources on the FPGA as the initial processor array by utilizing the processor array template with the highest matching degree with the plurality of sub-modules.
2. The method according to claim 1, wherein the simulated acceleration mode further comprises a transaction-level simulated acceleration mode and/or a prototype simulated acceleration mode, the method further comprising: Responding to the simulation acceleration mode being switched from a periodic accurate simulation acceleration mode to a transaction-level simulation acceleration mode or a prototype simulation acceleration mode, storing a current simulation state, mapping the simulation state into state information which can be identified by a physical unit in the FPGA according to a mapping relation database, wherein the mapping relation database records the mapping relation between the simulation state and the state information; and converting at least one part of the RTL code into a gate-level netlist, mapping the gate-level netlist onto the FPGA, and transmitting the state information to a physical unit corresponding to hardware resources in the FPGA for simulation.
3. The method according to claim 1, wherein the simulated acceleration mode further comprises a transaction-level simulated acceleration mode and/or a prototype simulated acceleration mode, the method further comprising: Responding to the simulation acceleration mode, switching the transaction-level simulation acceleration mode or the prototype simulation acceleration mode into a periodic accurate simulation acceleration mode, storing a current simulation state, and mapping the simulation state into state information which can be identified by the initial processor array according to a mapping relation database, wherein the mapping relation database records the mapping relation between the simulation state and the state information; and extracting characteristics of the RTL codes, configuring the FPGA into an initial processor array according to the characteristics, and transmitting the state information to the initial processor array for simulation.
4. A method according to claim 2 or 3, wherein the method of constructing the mapping database comprises: when generating a gate-level netlist from the RTL code, storing the mapping relation between the RTL code and a physical unit on the FPGA; When the RTL code is mapped into the instruction stream, the mapping relation between the RTL code and a plurality of processor cores contained in the initial processor array is saved; And constructing the mapping relation database according to the mapping relation between the RTL codes and the physical units on the FPGA and the mapping relation between the RTL codes and the processor cores in the initial processor array.
5. The method of claim 1, wherein configuring hardware resources on the FPGA as the initial processor array using a processor array template that matches the plurality of sub-modules most closely further comprises: Mapping the RTL code into the instruction stream according to an instruction set used by the initial processor array, and acquiring the number of instructions contained in the instruction stream; Determining the distribution number of the processor array templates with the highest matching degree with each sub-module according to the instruction number, wherein the total hardware resource quantity occupied by the processor array templates distributed by the plurality of sub-modules is smaller than or equal to the total hardware resource quantity on the FPGA; And configuring hardware resources on the FPGA according to the processor array template with the highest matching degree of each sub-module and the distribution quantity thereof so as to obtain the initial processor array.
6. The method of claim 1, wherein configuring the FPGA to configure hardware resources on the FPGA to match an initial processor array of the plurality of sub-modules according to the characteristics of each of the plurality of sub-modules further comprises: Classifying a plurality of sub-modules with the feature similarity larger than a preset threshold value into the same simulation task cluster; Calculating the matching degree between each simulation task cluster and each processor array template, and obtaining the processor array template with the highest matching degree with each simulation task cluster, wherein the matching degree between the simulation task cluster and the processor array template is the sum of the matching degree between each sub-module in the simulation task cluster and the processor array template; And configuring hardware resources on the FPGA into the initial processor array by using a processor array template with highest matching degree with each simulation task cluster.
7. The method of claim 6, wherein configuring the FPGA to configure hardware resources on the FPGA to match an initial processor array of the plurality of sub-modules according to the characteristics of each of the plurality of sub-modules further comprises: Mapping RTL codes of all sub-modules in each simulation task cluster into an instruction stream according to an instruction set used by the initial processor array, and obtaining the instruction number of the instruction stream; calculating the distribution number of the processor array templates with highest matching degree of each simulation task cluster according to the instruction number; and determining the initial processor array according to the processor array template with the highest matching degree of the simulation task cluster and the distribution quantity of the processor array template.
8. The method of claim 7, wherein the assigned number of processor array templates with highest matching degree for each simulation task cluster satisfies the following condition: the total hardware resource amount of the processor array with the highest matching degree allocated by each simulation task cluster does not exceed the total hardware resource amount on the FPGA; And dividing the instruction number by the minimum distribution number of the processor array templates with the highest matching degree scores of the simulation task clusters, wherein the distribution number is an integer not less than one.
9. The method of claim 1, wherein the mapping the RTL code into an instruction stream according to the instruction set to download onto the initial processor array for emulation comprises: inputting a test case for simulation, and monitoring characteristics and simulation performance data of the test case, and reconfiguring the initial processor array when the test case is switched and/or the reduction amplitude of the simulation performance data exceeds a preset threshold value; Wherein the reconfiguring includes: suspending the current simulation and storing the simulation state of the initial processor array; acquiring characteristics of a current test case, and determining a reconfiguration processor array according to the characteristics of the current test case; configuring hardware resources of the FPGA into the reconfiguration processor array; And mapping the RTL code into an instruction stream according to an instruction set used by the reconfiguration processor array, and loading the simulation state into the reconfiguration processor array for simulation.
10. An apparatus for simulating an RTL code, comprising: The data acquisition module is used for acquiring RTL codes to be simulated; The device comprises a simulation acceleration module, a feature extraction module, a characteristic analysis module and a control module, wherein the simulation acceleration module is used for responding to a simulation acceleration mode to be selected as a cycle accurate simulation acceleration mode, decomposing the RTL code into a plurality of sub-modules and respectively extracting features of each sub-module, and the decomposing of the RTL code into the plurality of sub-modules comprises decomposing the RTL code into a plurality of word modules according to functional boundaries and interfaces of the RTL code, wherein the features comprise operator types, data bit widths, parallelism, memory access modes and control logic complexity; The dynamic configuration module is used for configuring the FPGA according to the characteristics of each of the plurality of sub-modules so as to configure hardware resources on the FPGA into an initial processor array matched with the plurality of sub-modules; The mapping simulation module is used for mapping the RTL code into an instruction stream and downloading the instruction stream onto the initial processor array for simulation, and the instruction stream is generated according to an instruction set used by the initial processor array; The dynamic configuration module is specifically configured to calculate a matching degree between the plurality of sub-modules and each processor array template in a simulation special processor array library, wherein the simulation special processor array library stores a plurality of processor array templates, the processor array templates are used for configuring hardware resources on an FPGA as corresponding processor cores, and the hardware resources on the FPGA are configured as the initial processor array by using the processor array template with the highest matching degree with the plurality of sub-modules.
11. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the simulation method of RTL code according to any one of claims 1 to 9.
12. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the simulation method of RTL code according to any of claims 1 to 9.
13. A server comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, characterized in that the processor executes the steps of the simulation method of RTL code according to any of claims 1 to 9 when the computer program is executed.
14. A simulation system of RTL code, comprising the server of claim 13 and an FPGA coupled thereto.

Description

RTL code simulation method and device, storage medium, computer program product, server and system Technical Field The present application relates to the field of integrated circuit design verification, and in particular, to an RTL code simulation method and apparatus, a storage medium, a computer program product, a server, and a system. Background In the Field of integrated circuit design and verification, when simulating a large-scale system-on-chip, the traditional software simulation utilizes a general processor array to simulate, has slow running speed, becomes a main bottleneck in a design verification process, and has three simulation acceleration modes in the prior art, namely Field-Programmable gate array (FPGA) prototype verification, adjustable FPGA verification and a special simulation accelerator. The FPGA prototype verification converts the whole integrated circuit design into a gate-level netlist and maps the gate-level netlist to the FPGA for simulation, so that the speed is extremely high, but the FPGA prototype verification does not have signal visibility, and the debugging is extremely difficult. The adjustable FPGA verifies that the read-back circuit of the FPGA is utilized to save and transmit the complete internal state of the design from the hardware execution to the software simulator, so that the adjustable FPGA has high visibility and hardware execution speed, but the signal is returned and then is repeatedly modified and debugged in a slower software simulation environment, and the debugging efficiency is still lower. The dedicated emulation accelerator maps the entire integrated Circuit design into a dedicated processor array for emulation, and achieves acceleration by compiling Register Transfer Level (RTL) code into software instructions, but its hardware architecture is fixed, usually with a custom Application Specific Integrated Circuit (ASIC), which is difficult to deeply optimize for a specific RTL code or test case. Therefore, how to consider simulation efficiency, signal visibility and hardware cost is a technical problem to be solved in the field. Disclosure of Invention The embodiment of the application aims to provide an RTL code simulation method which can reduce hardware cost under the condition of keeping higher simulation efficiency. In a first aspect, the present invention provides a method for simulating an RTL code, including: The method comprises the steps of obtaining an RTL code to be simulated, responding to a simulation acceleration mode to be selected as a period accurate simulation acceleration mode, decomposing the RTL code into a plurality of sub-modules, respectively extracting characteristics of each sub-module, configuring an FPGA according to the characteristics of each sub-module so as to configure hardware resources on the FPGA into an initial processor array matched with the sub-modules, mapping the RTL code into an instruction stream, and downloading the instruction stream onto the initial processor array for simulation, wherein the instruction stream is generated according to an instruction set used by the initial processor array. Optionally, the simulation acceleration mode further comprises a transaction-level simulation acceleration mode and/or a prototype simulation acceleration mode, the method further comprises responding to the fact that the simulation acceleration mode is switched from the cycle accurate simulation acceleration mode to the transaction-level simulation acceleration mode or the prototype simulation acceleration mode, storing the current simulation state, mapping the simulation state into state information which can be recognized by a physical unit in the FPGA according to a mapping relation database, recording the mapping relation between the simulation state and the state information in the mapping relation database, converting at least one part of RTL codes into a gate-level netlist, mapping the gate-level netlist to the FPGA, and transmitting the state information to the physical unit corresponding to a hardware resource in the FPGA for simulation. Optionally, the simulation acceleration mode further comprises a transaction-level simulation acceleration mode and/or a prototype simulation acceleration mode, the method further comprises responding to the fact that the simulation acceleration mode is switched to a cycle accurate simulation acceleration mode from the transaction-level simulation acceleration mode or the prototype simulation acceleration mode, storing a current simulation state, mapping the simulation state into state information identifiable by the initial processor array according to a mapping relation database, wherein the mapping relation database records the mapping relation between the simulation state and the state information, extracting characteristics of the RTL code, configuring an FPGA into the initial processor array according to the characteristics, and transmitting the state information to th