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CN-121578848-B - Reference voltage generation circuit for 12nm technology

CN121578848BCN 121578848 BCN121578848 BCN 121578848BCN-121578848-B

Abstract

The invention provides a reference voltage generating circuit for a 12nm process, which relates to the technical field of integrated circuits and comprises a first reference circuit, a second reference circuit and an amplifier, wherein the first reference circuit is used for generating a first reference voltage irrelevant to a power supply voltage through a resistor based on a current mirror structure by utilizing a gate-source voltage difference of two transistors, the second reference circuit is used for generating a stable reference current based on clamping of the amplifier and generating a second reference voltage which is reduced along with temperature rise by utilizing positive temperature coefficient characteristics of the resistor, the amplifier is used for receiving the first reference voltage and outputting a first differential voltage irrelevant to the power supply voltage, or receiving the second reference voltage, compensating the second reference voltage by utilizing the positive temperature coefficient characteristics of the resistor and outputting a second differential voltage with stable amplitude and irrelevant to the temperature. In the reference voltage generating circuit, two kinds of reference circuits with emphasis work cooperatively to provide local optimal references for different parts of the system, so that the optimization of the system performance is realized on the whole.

Inventors

  • WEI NING
  • JIA HONGYI
  • WEI QIN

Assignees

  • 西安智多晶微电子有限公司

Dates

Publication Date
20260508
Application Date
20260129

Claims (8)

  1. 1. A reference voltage generation circuit for a12 nm process, comprising: A first reference circuit for generating a first reference voltage independent of a power supply voltage through a resistor by using a gate-source voltage difference of two transistors based on a current mirror structure; A second reference circuit for generating a stable reference current based on clamping of the amplifier and generating a second reference voltage decreasing with an increase in temperature by using a positive temperature coefficient characteristic of the resistor; The amplifier is used for receiving the first reference voltage and outputting a first differential voltage which is irrelevant to the power supply voltage, or receiving the second reference voltage, compensating the second reference voltage by utilizing the positive temperature coefficient characteristic of a resistor and outputting a second differential voltage which is stable in amplitude and is irrelevant to temperature; The first reference circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a first adjustable resistor, a first capacitor and a second capacitor, wherein the drain electrode of the first transistor is connected with the drain electrode of the fifth transistor, the gate electrode of the eighth transistor is connected with the drain electrode of the seventh transistor, the source electrode of the first transistor is connected with the drain electrode and the gate electrode of the sixth transistor, the gate electrode of the ninth transistor is connected with the gate electrode of the ninth transistor, the source electrode of the twenty-fourth transistor is connected with one end of the twenty-fourth adjustable resistor, the source electrode of the thirteenth transistor is connected with the source electrode of the thirteenth transistor, the drain electrode of the twenty-fifth transistor, the drain electrode of the twenty-seventh transistor is connected with the drain electrode of the twenty-seventh transistor, the drain electrode of the twenty-seventh transistor is connected with the drain electrode of the twenty-eighth transistor is connected with the drain electrode of the twenty-seventh transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the fifth transistor, the source electrode of the fifth transistor is connected with the drain electrode of the sixth transistor, the source electrode of the sixth transistor is connected with the other end of the first adjustable resistor, the source electrode of the eighth transistor is connected with the drain electrode of the ninth transistor, the gate electrode of the tenth transistor is input with a first delay signal, the drain electrode of the eleventh transistor is connected with the source electrode of the twelfth transistor, the drain electrode of the twelfth transistor is connected with the drain electrode and the gate electrode of the thirteenth transistor, one end of the first capacitor, one end of the second capacitor, the source electrode of the fourteenth transistor and the drain electrode of the fifteenth transistor, the other end of the first capacitor and the other end of the second capacitor are connected with the ground terminal, the gate electrode of the fourteenth transistor is input with a positive signal, the gate electrode of the fifteenth transistor is input with a negative signal, the drain electrode of the fourteenth transistor is connected with the source electrode of the fifteenth transistor and outputs the first reference voltage, the drain electrode of the twenty-fourth transistor is connected with the source electrode of the twenty-fourth transistor, the drain electrode of the twenty-sixth transistor is connected with the drain electrode of the twenty-fifth transistor is connected with the twenty-drain electrode of the twenty-fifth transistor; The second reference circuit comprises a twenty eighth transistor, a twenty ninth transistor, a thirty-first transistor, a second adjustable resistor, an operational amplifier, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor and a voltage generating circuit, wherein the non-inverting input end of the operational amplifier is connected with the drain electrode and the grid electrode of the twenty eighth transistor and one end of the second adjustable resistor, the inverting input end of the operational amplifier is connected with the output end of the voltage generating circuit and one end of the ninth capacitor, the output end of the operational amplifier is connected with one end of the tenth capacitor, the grid electrode of the twenty ninth transistor, one end of the eleventh capacitor, one end of the thirty-first transistor, the source electrode of the thirty-first transistor and the drain electrode of the thirty-first transistor, the other end of the second adjustable resistor is connected with the drain electrode of the twenty-eighth transistor, the other end of the ninth capacitor, the other end of the eleventh capacitor, the other end of the twelfth capacitor and the drain electrode of the thirty-first transistor are connected with the drain electrode of the thirty-first transistor, the thirty-second reference signal is negatively inputted to the drain electrode of the thirty-first transistor.
  2. 2. The reference voltage generating circuit for a 12nm process of claim 1, wherein the first reference circuit further comprises a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty first transistor, a second twenty transistor, a first inverter, a second inverter, a third capacitor, and a fourth capacitor, wherein, The source electrode of the sixteenth transistor is connected with the source electrode of the seventeenth transistor, the drain electrode of the twenty-first transistor and the drain electrode of the twenty-second transistor and is connected with the power supply voltage end, the grid electrode of the sixteenth transistor is connected with the grid electrode of the twentieth transistor and is input with a second delay signal, and the drain electrode of the sixteenth transistor is connected with the drain electrode of the seventeenth transistor, the drain electrode of the eighteenth transistor and the input end of the first inverter; a grid electrode of the seventeenth transistor is connected with the output end of the second inverter and the grid electrode of the nineteenth transistor; a gate of the eighteenth transistor inputs an enable signal, and a source of the eighteenth transistor is connected to a drain of the nineteenth transistor; a source electrode of the nineteenth transistor is connected with a drain electrode of the twentieth transistor; the source electrode of the twentieth transistor is connected with the ground terminal; The grid electrode of the twenty-first transistor is connected with the output end of the first inverter and the grid electrode of the twenty-first transistor, and the source electrode of the twenty-first transistor is connected with the drain electrode of the twenty-fourth transistor and the grid electrode of the first transistor; the source electrode of the twenty-seventh transistor is connected with the drain electrode of the twenty-seventh transistor; The grid electrode of the twenty-fourth transistor is connected with one end of a third capacitor, one end of a fourth capacitor and the input end of a third inverter, the output end of the third inverter is connected with the input end of the second inverter, and the other end of the third capacitor and the other end of the fourth capacitor are both connected with a grounding end.
  3. 3. The reference voltage generating circuit for a12 nm process of claim 2, further comprising a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor, wherein, The fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are sequentially connected in series, an enabling signal is input to the input end of the fourth inverter, the second delay signal is output to the output end of the fifth inverter, and the first delay signal is output to the output end of the seventh inverter; One end of the fifth capacitor is connected with the output end of the fourth inverter, the other end of the fifth capacitor is connected with the grounding end, one end of the sixth capacitor is connected with the output end of the fifth inverter, the other end of the sixth capacitor is connected with the grounding end, one end of the seventh capacitor is connected with the output end of the sixth inverter, the other end of the seventh capacitor is connected with the grounding end, and one end of the eighth capacitor is connected with the output end of the seventh inverter, and the other end of the eighth capacitor is connected with the grounding end.
  4. 4. The reference voltage generating circuit for a 12nm process according to claim 1, wherein the voltage generating circuit comprises N resistors, N-1 transfer gates, and a thirty-first transistor, N being a positive integer greater than or equal to 2, The N resistors are sequentially connected in series, one end of the 1 st resistor is connected with a power supply voltage end, one end of the N resistor is connected with the drain electrode of the thirty-second transistor, the grid electrode of the thirty-second transistor inputs a forward signal, and the source electrode of the thirty-second transistor is connected with a grounding end; the input end of each transmission gate is connected between two adjacent resistors, the first control end inputs a first control signal, the second control end inputs a second control signal, and the output end is connected with the inverting input end of the operational amplifier.
  5. 5. The reference voltage generating circuit for a 12nm process according to claim 1,2 or 4, further comprising an eighth inverter and a ninth inverter, wherein, The input end of the eighth inverter is input with a selection signal, the output end of the eighth inverter is connected with the input end of the ninth inverter and outputs the negative signal, and the output end of the ninth inverter outputs the positive signal.
  6. 6. The reference voltage generating circuit for a 12nm process of claim 1, wherein the amplifier comprises a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a third adjustable resistor, and a fourth adjustable resistor, wherein, The grid electrode of the thirty-fourth transistor is connected with the output end of the first reference circuit and the output end of the second reference circuit, the source electrode of the thirty-fourth transistor is connected with the ground end, and the drain electrode of the thirty-fourth transistor is connected with the source electrode of the thirty-third transistor and the source electrode of the thirty-fifth transistor; A first signal is input to the grid electrode of the thirteenth transistor, and the drain electrode of the thirty-third transistor is connected with one end of the fourth adjustable resistor and outputs a first voltage; the grid electrode of the thirty-fifth transistor is input with a second signal, and the drain electrode of the thirty-fifth transistor is connected with one end of a third adjustable resistor and outputs a second voltage; The other end of the third adjustable resistor and the other end of the fourth adjustable resistor are both connected with a power supply voltage end.
  7. 7. The reference voltage generation circuit for a 12nm process of claim 6 wherein the amplitude of the differential voltage output by the amplifier is: Wherein, the At the time of the first voltage level, At the time of the second voltage level, As the current of the thirty-fourth transistor, Is the resistance value of the third adjustable resistor, The resistance value of the fourth adjustable resistor, In order for the carrier mobility to be such that, Is the capacitance per unit area of the gate oxide layer, For the channel width of the thirty-fourth transistor, For the channel length of the thirty-fourth transistor, For the gate terminal voltage of the thirty-fourth transistor, Is the threshold voltage of the thirty-fourth transistor.
  8. 8. The reference voltage generating circuit for a 12nm process of claim 1, wherein the amplifier comprises a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a fifth adjustable resistor, a sixth adjustable resistor, a first resistor, and a thirteenth capacitor, wherein, The source electrode of the thirty-sixth transistor and the source electrode of the thirty-seventh transistor are both connected with a grounding end, the drain electrode of the thirty-sixth transistor is connected with one end of a thirteenth capacitor, one end of a first resistor and the source electrode of the thirty-eighth transistor, and the source electrode of the thirty-seventh transistor is connected with the other end of the thirteenth capacitor, the other end of the first resistor and the source electrode of the thirty-ninth transistor; a first signal is input to the grid electrode of the thirty-ninth transistor, and the drain electrode of the thirty-ninth transistor is connected with one end of the sixth adjustable resistor and outputs a first voltage; A second signal is input to the grid electrode of the thirty-eighth transistor, and the drain electrode of the thirty-eighth transistor is connected with one end of the fifth adjustable resistor and outputs a second voltage; The other end of the fifth adjustable resistor and the other end of the sixth adjustable resistor are both connected with a power supply voltage end.

Description

Reference voltage generation circuit for 12nm technology Technical Field The invention belongs to the technical field of integrated circuits, and particularly relates to a reference voltage generating circuit for a 12nm process. Background With the rapid development of data-intensive applications such as cloud computing, ethernet, mobile internet, artificial intelligence, etc., the desire for high-speed information transmission is increasing. Serializer/Deserializer (SerDes) is a core physical layer interface for data interconnect, which is continually pursuing higher data transmission rates, while the challenges facing signal integrity become greater. In high-speed SerDes systems, the accuracy and stability of the reference voltage (Voltage Reference, vref) directly determine the performance of the critical analog circuits, which are the "heartbeats" and "scales" that the entire link works reliably. In one aspect, the reference voltage precisely controls the transmit side (TX) differential output swing of the SerDes. The transmitting Terminal (TX) of SerDes typically drives the output differential signal through a current source set by a reference voltage, which small fluctuations directly result in a change in the amplitude of the output signal. The too small voltage swing can reduce the signal-to-noise ratio of the receiving end and obviously improve the error rate, and the too large swing can cause unnecessary power consumption and electromagnetic interference and violate strict system power consumption and radiation standard. Thus, an extremely stable, accurate reference is required to define this differential swing. The output amplitude is irrelevant to the temperature, the amplitude of the transmitted signal can be ensured to be constant at different temperatures, which is important to meet the amplitude specification of the high-speed interface, and the problems of misjudgment of a receiving end caused by amplitude attenuation at high temperature or electromagnetic interference (Electromagnetic Interference, EMI) caused by overlarge amplitude at low temperature are prevented. On the other hand, serdes circuits are typically high-speed, large switching noise environments, where high frequency noise on the power supply can easily couple into the reference output, resulting in high frequency ripple on the reference voltage. The Receiver (RX) of a SerDes typically includes a receiver signal decision module, such as a Sampler (Sampler) or comparator (comparator), that samples the receiver signal using a high-speed clock, and if the high-frequency noise on the power supply is directly coupled to a reference buffer that provides Vref to the Sampler, this time a signal of small amplitude (at the decision edge) may be determined to be "1" due to the jitter of the threshold, and the next time it is determined to be "0". This corresponds to the introduction of vertical noise, which directly reduces the sensitivity of the receiver. Even if the transmitted eye pattern is open, the receiving end may generate an error code due to the instability of the self-decision threshold. This is fatal to a communication system pursuing an extremely low error rate. Based on the above, the performance of many critical modules in SerDes is highly dependent on their internal bias voltages and bias currents. The prior art typically uses a conventional bandgap reference voltage source to generate a temperature independent reference voltage of about 1.25V, and a self-biasing op-amp and start-up circuit is typically used to construct a supply voltage independent bias point in order to make the reference voltage independent. However, at 12nm process, the core supply voltage may be as low as 0.8V or less, whereas the conventional bandgap reference voltage itself is about 1.25V, which is beyond the range of the supply voltage, making it impossible to directly operate. Although low voltage bandgap structures exist, they are generally more complex and more sensitive to matching and noise. Furthermore, to achieve good matching and low noise, the core resistor and transistors (Bipolar Junction Transistor, BJT) in conventional bandgap reference voltage sources typically require large size, and large area analog circuits can significantly increase the manufacturing cost of the chip. In addition, process fluctuations (e.g., linewidth, doping concentration) at the 12nm node have a great impact on circuit performance, and the accuracy of circuit simulation models provided by wafer foundries at extreme corners, especially at sub-threshold regions and high/low temperatures, may be subject to uncertainty. Meanwhile, at 12nm process, the threshold voltage of MOSFET is not scaled down, resulting in very tight voltage redundancy. Therefore, how to realize a reference voltage generation circuit with an amplifier output amplitude independent of temperature and a reference voltage generation circuit independent of a power supply voltage under a 12nm pro