CN-121579294-B - Memory bank installation self-checking method

Abstract

The invention discloses a memory bank installation self-checking method, and belongs to the technical field of computer storage equipment detection. According to the method, through separating test signals adapting to the working state of the memory, an incident signal and a reflected signal are obtained, the voltage of the incident signal and the reflected signal is collected and converted into digital information, the actual impedance and deviation of a link between a reflection coefficient and each detection frequency point are calculated, a detection result is generated after deviation threshold comparison is set, abnormal information is analyzed, a re-plugging or replacement prompt is sent out, and meanwhile the result is synchronized to a memory training flow. The method realizes the accurate detection of the installation state of the memory bank and the link impedance, timely checks the problem of poor contact caused by vibration or improper installation, reduces equipment operation faults, optimizes the memory training effect, and improves the equipment operation stability and maintenance convenience.

Inventors

• CHEN HANG

Assignees

• 四川华鲲振宇智能科技有限责任公司

Dates

Publication Date

20260508

Application Date

20260126

Claims (9)

1. 1. The memory bank installation self-checking method is characterized by comprising the following steps: S1, separating a test signal which is adaptive to the working state of a memory to obtain an incident signal and a reflected signal, collecting voltages corresponding to the two signals, and converting the voltages into digital information to obtain complete voltage data covering all detection frequency points; S2, calculating a reflection coefficient according to the ratio of the incident signal voltage to the reflected signal voltage, substituting the reflection coefficient into a reflection method impedance calculation formula and combining with a link design impedance to obtain a link actual impedance corresponding to each detection frequency point, and then calculating the deviation between the link actual impedance and the link design impedance; S3, setting a deviation threshold value based on a link design standard and a transmission line impedance change rule, and comparing impedance deviation of each frequency point with the deviation threshold value one by one to generate an impedance detection result comprising impedance values of each frequency point, deviation data and overall link impedance evaluation; S4, analyzing the impedance detection result, identifying abnormal conditions exceeding the deviation threshold, determining link and frequency point information corresponding to the abnormal conditions, sending out a prompt of re-plugging or replacing the related memory bank, and synchronizing the impedance detection result to the memory training flow; Wherein step S1 comprises the sub-steps of: S1.1, determining a detection frequency point range based on a memory working frequency, generating a frequency sweep signal covering the frequency point range, and adapting the frequency sweep signal to a memory working state; S1.2, carrying out separation treatment on the sweep frequency signal to obtain an incident signal and a reflected signal; s1.3, respectively acquiring voltages corresponding to the incident signal and the reflected signal, and converting the acquired analog voltage signal into digital information to form voltage data covering all detection frequency points.
2. 2. The method according to claim 1, characterized in that step S2 comprises the sub-steps of: S2.1, dividing the reflected signal voltage under each frequency point by the incident signal voltage by taking each detection frequency point as a unit to obtain a reflection coefficient corresponding to each frequency point; s2.2, substituting the reflection coefficient of each frequency point into a reflection method impedance calculation formula, combining with a preset link design impedance, and obtaining the link actual impedance corresponding to each frequency point through logic operation; s2.3, calculating deviation between the actual impedance of the link and the designed impedance of the link of each frequency point by taking the designed impedance of the link as a reference, and recording deviation data of each frequency point.
3. 3. The method according to claim 1, characterized in that step S3 comprises the sub-steps of: s3.1, setting a deviation threshold value for distinguishing normal impedance from abnormal impedance by combining a link design standard, a transmission line impedance change rule and an actual application scene; S3.2, according to the sequence of detecting the frequency points, comparing the impedance deviation recorded by each frequency point with a deviation threshold value respectively, and marking the comparison result of each frequency point; S3.3, summarizing the impedance values, deviation data and comparison results of all the frequency points, generating an impedance detection result containing the overall link impedance evaluation, and determining whether the overall link is abnormal.
4. 4. The method according to claim 1, characterized in that step S4 comprises the sub-steps of: S4.1, extracting frequency point information marked as abnormal from an impedance detection result, and associating a link identifier corresponding to the abnormal frequency point with a physical connection path; s4.2, positioning a memory bank corresponding to the link according to link information associated with the abnormal frequency point; S4.3, sending a prompt containing the association information of the abnormal memory bank and operation guide, wherein the operation guide is re-plugging or replacing; S4.4, synchronizing the complete impedance detection result to the memory training process.
5. 5. The method according to claim 1, wherein in step S1.1, the generation of the sweep frequency signal defines a range of detection frequency points in combination with frequency requirements corresponding to different operation modes of the memory, and the amplitude and phase parameters of the sweep frequency signal are adapted to the operation state of the memory, so that the sweep frequency signal can truly reflect the transmission characteristics of the link signal when the memory is in operation.
6. 6. The method of claim 2, wherein in step S2.3, the actual impedance of the link corresponding to each frequency point and the designed impedance of the link are correspondingly matched before calculating the deviation, and then the deviation calculation is performed by adopting a statistical method, the statistical method comprises average deviation and standard deviation, the absolute value of the impedance difference value of each frequency point is obtained when the average deviation is calculated, and then the average operation is performed on all the absolute values, and the square sum of the impedance difference values of each frequency point is obtained when the standard deviation is calculated, and then the square root is obtained after the average operation.
7. 7. A method according to claim 3, characterized in that in step S3.1, the setting of the deviation threshold comprises specifying a threshold and a proportional threshold, the tolerance range of the specified threshold reference link design determining a fixed value, the proportional threshold determining the threshold range based on a fixed proportion of the link design impedance, both setting being fine-tuned in combination with the transmission characteristic differences of the different frequency points.
8. 8. The method according to claim 4, wherein in step S4.4, when synchronizing the impedance detection result to the memory training process, format arrangement is performed on actual impedance data and deviation data of each frequency point link in the impedance detection result, data encapsulation is performed according to a protocol format identifiable by the memory training process, and then the data is transmitted to the memory training process.
9. 9. The method according to claim 1, wherein after step S4, the impedance detection result, the impedance value of each frequency point, the deviation data, the anomaly identification and the located memory bank information are stored, and the detection execution time, the corresponding device identification and the memory channel information are stored, and are organized according to the structured data format and then stored in a designated storage unit, so as to form a complete detection record.

Description

Memory bank installation self-checking method Technical Field The invention relates to the technical field of computer storage equipment detection, in particular to a memory bank installation self-checking method. Background With popularization and performance upgrading of data centers, servers and various computing devices, the memory bank is used as a core storage component, the application scene is increasingly wide, and the requirements on installation stability and link transmission quality are continuously improved. At present, the installation of memory strip mainly relies on manual operation and mechanical jig to assist two kinds of modes, realizes the fixed of physical aspect through structural design such as buckle locking, ensures the preliminary connection of memory strip and mainboard slot. In the product delivery stage, manufacturers verify the whole running state of the equipment by means of pressure test, power-on self-test and the like to confirm the normal basic functions of core components such as memory strips and the like, partial equipment systems also have memory initialization detection functions to identify obvious faults such as particle failure, complete installation failure and the like, and partial monitoring mechanisms can record the conditions such as bit overturning, CE abnormality, UCE abnormality and the like in the running process of the equipment, so that post references are provided for fault detection. The technical means and the application mode jointly form the current industry situation in the field of installation and detection of the current memory bank, and a certain guarantee is provided for basic operation of equipment. However, the technical problems that are difficult to avoid in the practical application still exist in the prior art system. In links such as transportation, loading and migration, the equipment such as server and the like can be inevitably influenced by external forces such as vibration and jolt, and poor contact between a memory bank and a PIN of a slot can possibly be caused, and the poor contact is often not recognized by a traditional structure fixed inspection or initialization flow, so that the equipment is suddenly shut down due to abnormal link impedance after running for a period of time, and service continuity is seriously influenced. The existing memory initialization flow can only screen completely invalid or obviously uninstalled memory strips, has no effective detection means for the condition that the initialization is passed but the link signal transmission quality is poor, can not accurately judge whether the link impedance is in a normal range, and the abnormal monitoring in operation belongs to a post alarm mechanism, can only record related information after the fault occurs, can not pre-judge potential risks in advance, and needs maintenance personnel to continuously pay attention to log data, so that the maintenance cost is high. In addition, the prior art lacks quantitative detection capability for the impedance characteristic of the link, and the link state is not analyzed through systematic processes such as signal separation, voltage acquisition, impedance calculation and threshold ratio, so that impedance abnormality caused by poor contact, vibration interference and the like cannot be positioned in time, early warning cannot be sent out in advance, maintenance operation is guided, and the running stability and reliability of equipment are severely restricted. Disclosure of Invention The invention aims to overcome the defects of the prior art and provides a memory bank installation self-checking method. The aim of the invention is realized by the following technical scheme: The method for self-checking the installation of the memory bank comprises the following steps: S1, separating a test signal which is adaptive to the working state of a memory to obtain an incident signal and a reflected signal, collecting voltages corresponding to the two signals, and converting the voltages into digital information to obtain complete voltage data covering all detection frequency points; S2, calculating a reflection coefficient according to the ratio of the incident signal voltage to the reflected signal voltage, substituting the reflection coefficient into a reflection method impedance calculation formula and combining with a link design impedance to obtain a link actual impedance corresponding to each detection frequency point, and then calculating the deviation between the link actual impedance and the link design impedance; S3, setting a deviation threshold value based on a link design standard and a transmission line impedance change rule, and comparing impedance deviation of each frequency point with the deviation threshold value one by one to generate an impedance detection result comprising impedance values of each frequency point, deviation data and overall link impedance evaluation; S4, analyzing the impedance detection