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CN-121580928-B - Code processing method and device of integrated circuit, electronic equipment and storage medium

CN121580928BCN 121580928 BCN121580928 BCN 121580928BCN-121580928-B

Abstract

The application provides a code processing method, a device, electronic equipment and a storage medium of an integrated circuit, wherein the method comprises the steps of obtaining source codes, constructing a structured packaging unit tree based on the source codes, carrying out packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object, instantiating the structured object to obtain a hardware description language module, and carrying out code generation based on the connection instruction and the hardware description language module in response to receiving the connection instruction to obtain connection codes, wherein the connection instruction comprises a connection relation between sub-modules in the integrated circuit, the connection codes indicate signal transmission paths between the sub-modules in the integrated circuit, and the connection codes are hardware description language codes. The application can improve the efficiency of the connection of the signal transmission paths between the modules in the integrated circuit design.

Inventors

  • WANG LIAN

Assignees

  • 上海东方算芯科技有限公司

Dates

Publication Date
20260512
Application Date
20260126

Claims (8)

  1. 1. A method of code processing for an integrated circuit, the method comprising: Acquiring source codes, wherein the source codes comprise parameter information of sub-modules in an integrated circuit, and the source codes are register transmission level codes; carrying out grammar analysis on the parameter information of the source code to obtain structural information, wherein the structural information comprises a sub-module name, a port name, an interface type and an interface parameter; Converting the structured information into a structured list, wherein the structured list is an operable intermediate data structure in a computer memory; constructing a root node of a structured packing unit tree; extracting information of sub-modules from the structured list, performing the following processing for each of the sub-modules: Splitting the port name of the sub-module to obtain a plurality of sub-fields; taking each sub-field as a sub-node; According to the arrangement sequence of the plurality of subfields, connecting each of the subfields to obtain a tree path corresponding to the submodule; Connecting a starting node of each tree path with the root node to obtain the structured packing unit tree, wherein the starting node is used for representing a first subfield in the port name; Packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; Instantiating the structured object to obtain a hardware description language module; and responding to receiving a connection instruction, and generating codes based on the connection instruction and a hardware description language module to obtain connection codes, wherein the connection instruction comprises a connection relation between the sub-modules in the integrated circuit, the connection codes indicate signal transmission paths between the sub-modules in the integrated circuit, and the connection codes are hardware description language codes.
  2. 2. The method according to claim 1, wherein the encapsulating the structured packing element tree according to the high-level hardware description language to obtain a structured object comprises: Carrying out standardization processing on the structured packaging unit tree to obtain a standardized structured packaging unit tree; and mapping the standardized port names in the structured packing unit tree into member variables in an object programming language according to a high-level hardware description language to obtain a structured object.
  3. 3. The method according to claim 2, wherein the normalizing the structured packing element tree to obtain the normalized structured packing element tree comprises: matching the child nodes of the structured packing unit tree according to a preset bus protocol library, and marking the child nodes based on the matched interface types; Determining the function type of a tree path of the structured packing unit tree according to a first subfield in a port name, and merging starting nodes of the tree path with the same function type, wherein the starting nodes are used for representing the first subfield in the port name; according to a preset rule, determining a non-standardized sub-field in the structured packing unit tree, and replacing the non-standardized sub-field with a standardized sub-field; and taking the replaced structured packing unit tree as the standardized structured packing unit tree.
  4. 4. The method of claim 1, wherein instantiating the structured object results in a hardware description language module comprising: importing a hardware description primitive library and a standard hardware library in an operation environment of the high-level hardware description language, and defining a hardware module class based on the hardware description primitive library and the standard hardware library; in the hardware module class, respectively creating module instance objects of all sub-modules in the integrated circuit based on the structured objects; And constructing the connection between the module instance objects according to the high-level hardware description language to form the hardware description language module.
  5. 5. The method of claim 1, wherein the generating, in response to receiving the connection instruction, a code based on the connection instruction and a hardware description language module, to obtain a connection code, comprises: converting script files carried by the connection instruction to obtain a connection relation in a hardware description language form; determining a signal transmission path between ports of the submodule in the integrated circuit based on the connection relation; And calling the hardware description language module to generate the connection code according to the signal transmission path and the assignment key.
  6. 6. A code processing apparatus for an integrated circuit, the apparatus comprising: The data acquisition module is used for acquiring source codes, wherein the source codes comprise parameter information of submodules in an integrated circuit, and the source codes are register transmission level codes; the code packaging module is used for carrying out syntax analysis on the parameter information of the source code to obtain structural information, wherein the structural information comprises a sub-module name, a port name, an interface type and an interface parameter; Converting the structured information into a structured list, wherein the structured list is an operable intermediate data structure in a computer memory; constructing a root node of a structured packing unit tree; extracting information of sub-modules from the structured list, performing the following processing for each of the sub-modules: Splitting the port name of the sub-module to obtain a plurality of sub-fields; taking each sub-field as a sub-node; According to the arrangement sequence of the plurality of subfields, connecting each of the subfields to obtain a tree path corresponding to the submodule; Connecting a starting node of each tree path with the root node to obtain the structured packing unit tree, wherein the starting node is used for representing a first subfield in the port name; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; And the code generation module is used for responding to the received connection instruction, generating codes based on the connection instruction and the hardware description language module to obtain connection codes, wherein the connection instruction comprises a connection relation between the sub-modules in the integrated circuit, the connection codes indicate signal transmission paths between the sub-modules in the integrated circuit, and the connection codes are hardware description language codes.
  7. 7. An electronic device, the electronic device comprising: A memory for storing computer executable instructions or computer programs; A processor for implementing the code processing method of an integrated circuit according to any one of claims 1 to 5 when executing computer executable instructions or computer programs stored in said memory.
  8. 8. A computer-readable storage medium storing computer-executable instructions or a computer program, wherein the computer-executable instructions or the computer program when executed by a processor implement the code processing method of an integrated circuit according to any one of claims 1 to 5.

Description

Code processing method and device of integrated circuit, electronic equipment and storage medium Technical Field The present application relates to electronic design automation technology, and in particular, to a method and apparatus for processing codes of an integrated circuit, an electronic device, and a storage medium. Background Electronic Design Automation (EDA) is a technology that utilizes Computer Aided Design (CAD) software to automate the process of Very Large Scale Integrated (VLSI) and related electronic system design. In related art electronic design automation flows, module connectivity typically relies on manual writing of hardware description languages (e.g., verilog or System Verilog) or assisted generation of specific tools. With the rapid expansion of the design scale of integrated circuits, hardware construction frames based on high-level programming languages gradually become a new trend in the design field due to high abstraction and development efficiency. However, significant amounts of Register Transfer Level (RTL) code remain in the current chip design ecology. When the RTL module is integrated into a high-level language environment for top-level interconnection, it is difficult to map directly to a structured object (e.g., bundle) in the high-level language. This means that a designer must manually write a large number of black box (BlackBox) packaging codes to reconstruct the interface structure, which is cumbersome and repetitive. Secondly, RTL modules from different sources often have inconsistent naming styles, and automation tools are difficult to intelligently match across naming differences, so that designers still need to write thousands of assignment codes connected line by line at the top layer, which is low in efficiency, and connection errors are easily introduced, so that the design efficiency of an integrated circuit is influenced. Disclosure of Invention The embodiment of the application provides a code processing method, a device, electronic equipment and a storage medium of an integrated circuit, which can improve the efficiency of connection of signal transmission paths among modules in the design of the integrated circuit. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a code processing method of an integrated circuit, which comprises the following steps: Acquiring source codes, wherein the source codes comprise parameter information of sub-modules in an integrated circuit, and the source codes are register transmission level codes; constructing a structured packing unit tree based on the source code, wherein the structured packing unit tree comprises a root node and sub-nodes, and the sub-nodes represent sub-fields of port names in the parameter information; Packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; Instantiating the structured object to obtain a hardware description language module; and responding to receiving a connection instruction, and generating codes based on the connection instruction and a hardware description language module to obtain connection codes, wherein the connection instruction comprises a connection relation between the sub-modules in the integrated circuit, the connection codes indicate signal transmission paths between the sub-modules in the integrated circuit, and the connection codes are hardware description language codes. The embodiment of the application provides a code processing device of an integrated circuit, which comprises: The data acquisition module is used for acquiring source codes, wherein the source codes comprise parameter information of submodules in an integrated circuit, and the source codes are register transmission level codes; The code packaging module is used for constructing a structured packaging unit tree based on the source code, wherein the structured packaging unit tree comprises a root node and a child node, and the child node represents a child field of a port name in the parameter information; And the code generation module is used for responding to the received connection instruction, generating codes based on the connection instruction and the hardware description language module to obtain connection codes, wherein the connection instruction comprises a connection relation between the sub-modules in the integrated circuit, the connection codes indicate signal transmission paths between the sub-modules in the integrated circuit, and the connection codes are hardware description language codes. An embodiment of the present application provides an electronic device, including: A memory for storing computer executable instructions or computer programs; And the processor is used for realizing the code processing method of the integrated circuit when executing the computer executable instructions or the computer programs stored in the memory. T