Search

CN-121580958-B - Large-area AI embedded computing system and glass panel level integrated packaging method

CN121580958BCN 121580958 BCN121580958 BCN 121580958BCN-121580958-B

Abstract

The invention discloses a large-area AI embedded computing system, which relates to the technical field of semiconductor packaging, and comprises sensing, computing and facility functional layers which are sequentially stacked from top to bottom, wherein the sensing layer is used for receiving light incidence to be detected and generating sensing signals, the computing layer is used for carrying out data processing on the sensing signals and outputting data, the facility layer is used for providing energy and communication support for the system, each functional layer is independently arranged on a glass panel, an optical waveguide path and/or a vertical conductive path are arranged in the glass panel, optical I/O chips are integrated among the layers and packaged through three-dimensional stacking to form an interlayer optical interconnection network, so that cooperative interconnection of electric property and optics is realized, and high-speed and low-power consumption photoelectric data transmission is realized.

Inventors

  • WANG KAI
  • ZHANG PEIXUAN

Assignees

  • 合肥海纳知微高新技术有限公司

Dates

Publication Date
20260508
Application Date
20251021

Claims (10)

  1. 1. A large area AI embedded computing system, characterized in that, The device comprises a sensing layer, a calculating layer and a facility layer which are sequentially stacked from top to bottom, wherein the sensing layer is used for receiving light incidence to be detected and generating a sensing signal, the sensing signal enters the calculating layer for data processing and outputting data, the facility layer supports the sensing layer and the calculating layer to work through photoelectric interconnection, receives the data output by the calculating layer and transmits the data to external equipment; The sensing layer, the calculating layer and the facility layer are respectively and independently arranged on a glass panel, an optical waveguide path and/or a vertical conductive path are arranged in each glass panel, optical I/O chips are integrated between the layers, and the optical I/O chips are packaged through three-dimensional stacking to form an interlayer optical interconnection network for electrical and optical interconnection, and are used for realizing high-speed and low-power consumption photoelectric cooperative data transmission.
  2. 2. The large area AI embedded computing system of claim 1, wherein, The sensing layer includes an absorber and a detector; The detectors are laid on the glass panel of the sensing layer in a matrix mode to form a matrix detection unit, and the absorbers are laid on the matrix detection unit to receive light rays to be detected; The matrix detection unit is interconnected with the absorber to amplify and convert an incident optical signal into the sensing signal in the form of an electric signal, the sensing signal is transmitted to the optical I/O chip between the calculation layer and the sensing layer in a light conduction mode through the interlayer optical interconnection network, and the optical I/O chip performs photoelectric conversion and module communication of the calculation layer.
  3. 3. The large area AI embedded computing system of claim 1, wherein, The computing layer comprises a computing chip set consisting of an AI-FPGA module, a CPU module and a GPU module; the computing chip set is connected with the computing layer, the perception layer and the computing layer and the optical I/O chip between the facility layers and is used for optical and electrical communication connection between the computing layer and the perception layer and between the computing layer and the facility layer; The computing chip set of the computing layer receives the instruction of the facility layer and the sensing signal of the sensing layer through the optical I/O chip between layers, and is used for executing real-time data processing, machine learning reasoning and algorithm acceleration, and completing interlayer high-speed optical signal communication and photoelectric conversion through the optical I/O chip.
  4. 4. The large area AI embedded computing system of claim 1, wherein, The device comprises a facility layer, a power management module, a micro battery, a storage chip and a high-speed interface module, wherein the micro battery is arranged in a battery cavity of a glass panel of the facility layer and is electrically connected with the power management module, the storage chip and the high-speed interface module, and the high-speed interface module is communicated with the storage chip, the calculation layer, an optical I/O chip between the facility layer and external equipment to be accessed in a connecting way; the battery cavity is formed through dry etching, the miniature battery is embedded in the battery cavity, and a nickel sealing sheet covers the top of the battery cavity to encapsulate the miniature battery in the facility layer.
  5. 5. The large area AI embedded computing system of claim 4, The depth of the battery cavity is 250-350 mu m; the miniature battery is a solid-state thin film lithium battery with the thickness of 180-280 mu m and the energy density of 350 Wh/L; and the nickel sealing piece is covered on the top of the battery cavity, and is fused with the glass panel on the periphery of the battery cavity through nickel-glass laser ring welding, so that the resistance of a power supply path is reduced in a mode that the length of the power supply path is matched with the depth of the battery cavity.
  6. 6. The large area AI embedded computing system of claim 5, And a PMIC chip is embedded in the glass panel of the facility layer and is electrically connected with the miniature battery and the power management module, so that the power management module can perform module-level dynamic power supply scheduling by adjusting the dynamic voltage from positive 0.8V to negative 1.2V.
  7. 7. The large area AI embedded computing system of claim 1, wherein, Forming a glass through hole with the aperture less than or equal to 10 mu m on the glass panel, depositing a Ti/Cu composite seed layer in the hole wall, and filling copper in the glass through hole in an electroplating manner to form the vertical conductive path; The optical waveguide passage is arranged in an area within 15 mu m of the periphery of the structure of the glass through hole, and is a silicon nitride optical waveguide for reducing electromagnetic crosstalk and optical loss; and the glass through hole is provided with a TGV bonding pad, the optical I/O chip is flip-chip welded to the TGV bonding pad, senses optical communication information of the silicon nitride optical waveguide and converts the optical communication information into an electric signal, and forms electric communication through the vertical conductive path for realizing high-speed photoelectric signal conversion.
  8. 8. The large area AI embedded computing system of claim 3, The surface of the glass panel is bonded with a flexible film layer through hot pressing, and the flexible film layer is a polyimide flexible intermediate layer; and constructing Cu/Ni/Au multilayer wiring on the flexible film layer between the glass panel of the computing layer and the computing chip set, wherein electric signals of the computing chip set and the optical I/O chip are transmitted through the Cu/Ni/Au multilayer wiring.
  9. 9. A glass panel level integrated packaging method applied to the large-area AI embedded computing system of any one of claims 1 to 8, comprising the steps of: (1) Preparing optical waveguide paths and vertical conductive paths on the multi-layer glass panel respectively; (2) The system comprises a sensing layer manufacturing absorber, a sensing layer manufacturing detector, a computing layer manufacturing computing chip set, an optical I/O chip, a facility layer manufacturing power management module, a battery cavity, a storage chip and a high-speed interface module, wherein the sensing layer, the computing layer and the facility layer are respectively prepared; (3) The sensing layer, the calculating layer and the facility layer are stacked in sequence by adopting a high-precision alignment and 3D hybrid bonding process, so that photoelectric integrated interconnection is realized; (4) After the glass-glass hot-press bonding is adopted, a miniature battery is embedded in a battery cavity of a facility layer, and a nickel sealing sheet is welded in the battery cavity through nickel-glass laser ring welding, so that a packaging structure is formed.
  10. 10. The method of claim 9, wherein the glass panel level integrated package, The 3D hybrid bonding process comprises two stages of low-temperature bonding and high-temperature annealing: at the low-temperature bonding stage, at the temperature of less than or equal to 250 ℃, the glass panels of the sensing layer, the calculating layer and the facility layer are bonded with the flexible film in a hot-pressing way, then the optical I/O chip is welded, and finally the optical waveguide path and the optical I/O chip are packaged by using low-temperature curing epoxy resin; And in the high-temperature annealing stage, annealing and repairing the electroplating defects of the glass through hole in the H 2 atmosphere at the temperature of more than or equal to 300 ℃ to reduce the resistivity, and selectively annealing the computing chip set by infrared laser to avoid thermal damage to the packaged photoelectric device.

Description

Large-area AI embedded computing system and glass panel level integrated packaging method Technical Field The invention relates to the technical field of semiconductor packaging, in particular to a large-area AI embedded computing system and a glass panel level integrated packaging method. Background With the rapid development of emerging technologies such as Artificial Intelligence (AI), internet of things (IoT), and augmented/virtual reality (AR/VR), computing systems are evolving towards large-area, high pixel density, low power consumption, and embedded AI functionality integration, requiring multi-chip, multi-functional co-optimization on the same packaging platform. However, the conventional silicon-based semiconductor package has gradually encountered moore's law to alleviate system-level performance bottlenecks, namely continuous increase in chip size, increase in computation frequency, synchronous increase in high-speed signal transmission and thermal management requirements, so that it is difficult for the conventional package structure to achieve high computation power, low power consumption and reliability. In recent years, new technologies such as glass panel level packaging (PANEL LEVEL PACKAGING, PLP) and three-dimensional stacked packaging are proposed in the industry, and attempts are made to realize high-density integration of a multi-chip module by utilizing the insulation property, low parasitic capacitance and large area characteristics of a glass substrate, glass through holes (Through Glass Via, TGV) are used as a vertical interconnection structure penetrating through the glass substrate, compared with Through Silicon Vias (TSVs), parasitic capacitance can be effectively reduced, high-frequency signal transmission capacity is improved, the panel level packaging is considered by taking the manufacturing thought of a display panel as a reference, and efficient packaging of multi-chip and multi-passive devices is realized through fan-out wiring, so that balance between cost and integration level is hopeful. Despite the advances made in the above-described technology, there are significant shortcomings in existing advanced packaging schemes. The conventional silicon interposer packaging structure has the problems that the parasitic capacitance of the silicon interposer is high (more than about 50 fF) while the wiring density is improved, so that signal loss is remarkable during high-frequency operation, AI computing power output is limited, the conventional silicon substrate and optical glass substrate combination is used for realizing logic chip stacking, but the silicon substrate (CTE (approximately 2.6 ppm/°) and the optical glass substrate (CTE approximately 7 ppm/°) have large difference in thermal expansion coefficient, the bonding interface is easy to fail after thermal cycling, and in addition, the OLED display module is used for realizing heat dissipation and shock absorption through the high-heat-conduction metal plate and low-heat-conduction polymer layer combination, but the problems of surface or junction temperature exceeding 150 ℃, device performance degradation and the like still occur under a high-power density scene (> 3W), and obviously, the difference in material thermal physical characteristics and insufficient heat dissipation become core barriers for improving the reliability of three-dimensional integration. In addition, the current Through Silicon Via (TSV) packaging structure is still limited by signal transmission performance under high integration, high parasitic capacitance of a silicon interposer causes high-frequency signal distortion and bandwidth reduction, AI reasoning response is directly affected, thermal expansion coefficient mismatch (such as Cu vs SiLK) among silicon, glass and organic materials in the aspect of thermal reliability causes interface cracking and bonding stripping, and low heat conduction performance of an organic layer causes rapid temperature rise under high power, and frequency reduction or device failure is induced. Meanwhile, the complex multi-layer process and material combination also promote the manufacturing cost, and the manufacturing cost per square centimeter is too high, so that the popularization of the material in large-area low-cost commercial scenes is restricted. The prior art has at least the following technical problems that high-frequency signal transmission is still limited by parasitic capacitance and transmission loss, the requirements of a large-scale AI system are difficult to meet, the problems of low heat dissipation efficiency and reliability caused by multi-material thermal expansion mismatch are not solved effectively, and the popularization of glass panel level packaging in large-scale business is limited due to complex manufacturing process and high unit area cost. In summary, it is found that the prior art has at least the following technical problems: In the prior art, the high-frequency signal transm