CN-121585142-B - Multi-channel voltage converter, clock circuit thereof and power management chip

CN121585142BCN 121585142 BCN121585142 BCN 121585142BCN-121585142-B

Abstract

The invention provides a multichannel voltage converter, a clock circuit and a power management chip thereof, which comprise a reference clock circuit and a channel clock circuit, wherein in a discontinuous conduction mode, the channel clock circuit is used for determining a channel target sub-clock signal of a next period at a channel delay time after a channel target sub-clock signal of a current period is ended, and generating the channel clock signal of the next period based on the channel target sub-clock signal of the next period to obtain the channel clock signal with lower frequency so as to ensure stable output of each channel in light load. The channel clock circuits are controlled to be non-enabled in the phase-misplacement delay time after the channel target sub-clock signals enter the next period, and the other channel clock signals can be controlled to be invalid (low level) at the rising edge of one channel clock signal so as to generate the phase-misplacement channel clock signals, thereby ensuring that each channel works in the phase misplacement mode in a discontinuous conduction mode.

Inventors

LIU HAO
Han Nianpeng
WANG YIWEI
SHI LIJUAN
FANG YUJIE

Assignees

芯洲科技(北京)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260126

Claims (9)

1. The clock circuit of the multichannel voltage converter is characterized by comprising a reference clock circuit and N channel clock circuits, wherein N output ends of the reference clock circuit are connected with N input ends of each channel clock circuit in a one-to-one correspondence manner, and N is an integer greater than or equal to 2; the reference clock circuit is configured to generate a reference clock signal, and perform phase-shifting processing on the reference clock signal to obtain N sub-clock signals; When the channel working mode is a discontinuous conduction mode, determining a channel target sub-clock signal of a next period at a channel delay time after the channel target sub-clock signal of a current period is ended, generating a channel clock signal of the next period based on the channel target sub-clock signal of the next period, and controlling other channel clock circuits to be disabled within the phase-dislocation delay time after the channel target sub-clock signal enters the next period; Wherein, in each period, the channel clock signal is aligned with a rising edge of the channel target sub-clock signal, and the channel target sub-clock signal in the next period is a signal with the rising edge nearest to the channel delay time after the end of the current period in the N sub-clock signals; The system comprises a plurality of channel clock circuits, a reference clock circuit, a plurality of channel load detection circuits, a plurality of mode detection circuits and a plurality of control circuits, wherein each channel clock circuit comprises a clock selection circuit and a mode detection circuit, N input ends of the clock selection circuit are connected with N output ends of the reference clock circuit in a one-to-one correspondence manner, a first input end of the mode detection circuit is connected with the channel load detection voltage, a second input end of the mode detection circuit is connected with the detection reference voltage, and an output end of the mode detection circuit is connected with a control end of the clock selection circuit; the mode detection circuit is configured to determine a channel mode detection signal based on whether the channel load detection voltage is greater than the detection reference voltage; The clock selection circuit is configured to select one of the N sub-clock signals as the channel target sub-clock signal when the channel mode detection signal is a continuous conduction mode signal, and determine that the channel target sub-clock signal in a continuous conduction mode is the channel target sub-clock signal of a first period in the discontinuous conduction mode when the channel mode detection signal is a discontinuous conduction mode signal, and flip a channel delay time signal to be a sub-clock signal which reaches first rising edges of the N sub-clock signals after invalidation is determined as the channel target sub-clock signal of the next period in the current period of the discontinuous conduction mode.
2. The clock circuit of claim 1, wherein each channel clock circuit further comprises a clock determination circuit; the input end of the clock determining circuit is connected with the output end of the clock selecting circuit, and the control end of the clock determining circuit is connected with the phase-dislocation delay time signal; The clock determination circuit is configured to pull the channel clock signal high at a rising edge of the channel target sub-clock signal and pull the channel clock signal low after a duty cycle delay time when the phase-dislocation delay time signal is active.
3. The clock circuit of claim 2, wherein the clock selection circuit comprises N D flip-flops, n+1 or gates, nor gates, N switches, a first selector, and a second selector; The first input end of the first selector and the first input end of the second selector are connected with a power supply voltage, the second input end of the first selector is connected with the channel delay time signal, the second input end of the second selector is grounded, the control end of the first selector and the control end of the second selector are connected with a first gating signal, the output end of the first selector is connected with the reset ends of the N D triggers, and the output end of the second selector is connected with the first input end of the N+1th OR gate; The positive phase output ends of the N D flip-flops are connected with first input ends of a first OR gate to an N-th OR gate in a one-to-one correspondence manner, the second input ends of the first OR gate to the N-th OR gate are connected with the output ends of the NOR gate, the output ends of the first OR gate to the N-th OR gate are connected with the input ends of the N D flip-flops in a one-to-one correspondence manner, the positive phase output end of each D flip-flop is connected with one input end of the NOR gate, and the clock end of each D flip-flop is connected with the input end of a switch and one output end of the reference clock circuit; the second input end of the (n+1) th or gate of the (i) th channel clock circuit is connected with the positive phase output end of the (j) th D trigger, the output end of the (n+1) th or gate of the (i) th channel clock circuit is connected with the control end of the (j) th switch, the control ends of the remaining (N-1) switches are connected with the positive phase output ends of the remaining (N-1) D triggers in a one-to-one correspondence manner, and the output ends of the (N) switches are connected with the output end of the clock selection circuit; Wherein i is any integer greater than or equal to 1 and less than or equal to M, M is the channel number of the multi-channel voltage converter, j is any integer greater than or equal to 1 and less than or equal to N, j=1+ (i-1) N/M.
4. The clock circuit of claim 3, wherein the clock determination circuit comprises a third selector, a nand gate, a duty cycle delay, and a first D flip-flop; The first input end of the third selector and the input end of the first D trigger are connected with the power supply voltage, the second input end of the third selector is connected with the phase-dislocation delay time signal, the control end of the third selector is connected with a second gating signal, the output end of the third selector is connected with the first input end of the NAND gate, the second input end of the NAND gate is connected with the output end of the duty cycle delay device, and the output end of the NAND gate is connected with the reset end of the first D trigger; the clock end of the first D trigger is connected with the output end of the clock selection circuit, the positive phase output end of the first D trigger is connected with the clock output end of the channel clock circuit, and the negative phase output end of the first D trigger is connected with the input end of the duty cycle delayer.
5. The clock circuit of claim 4, wherein each channel clock circuit further comprises a pull-down resistor, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; The pull-down resistor is connected between the output end of the clock selection circuit and the ground, the clock end of the second D trigger is connected with the inverted output end of the first D trigger, the input end of the second D trigger is connected with the output end of the mode detection circuit, and the non-inverted output end of the second D trigger is connected with the input end of the third D trigger, the control end of the third selector and the input end of the fourth D trigger; The clock end of the third D trigger and the clock end of the fourth D trigger are connected with the output end of the clock selection circuit, the positive phase output end of the third D trigger is connected with the control end of the first selector and the control end of the second selector, the reset end of the fourth D trigger is connected with the phase-dislocation delay time signal, and the positive phase output end of the fourth D trigger is connected with the second input end of the first selector.
6. The clock circuit of any one of claims 1-5, wherein the channel clock circuit further comprises a clamp subtractor, a voltage-to-time conversion circuit, and a phase-dislocation delay; the non-inverting input end of the clamping subtracter is connected with the detection reference voltage, the inverting input end of the clamping subtracter is connected with the channel load detection voltage, the output end of the clamping subtracter is connected with the input end of the voltage-time conversion circuit, the reset end of the voltage-time conversion circuit is connected with the output end of the phase-shifting delay device, the input end of the phase-shifting delay device is connected with the clock output end of the channel clock circuit, the control end of the voltage-time conversion circuit is connected with the control output end of the clock selection circuit, and the output end of the voltage-time conversion circuit is connected with the reset end of the clock selection circuit; the clamp subtractor is configured to determine a differential voltage of the channel load detection voltage and the detection reference voltage; The phase-dislocation delayer is configured to delay the phase-dislocation delay time for the rising edge of the channel clock signal, and determine a transition reset signal; the voltage-to-time conversion circuit is configured to convert the differential voltage to the channel delay time to determine a channel delay time signal when the channel clock circuit is enabled, and to determine a phase-dislocation delay time signal based on the channel delay time signal and the transition reset signal.
7. The clock circuit of claim 6, wherein the voltage to time conversion circuit comprises a fifth D flip-flop, an RS flip-flop, an inverter, an and gate, a time comparator, a transistor, a current source, and a capacitor; The power supply voltage is connected with the non-inverting input end of the time comparator, the first polar plate of the capacitor and the first end of the transistor through the current source, the inverting input end of the time comparator is connected with the output end of the clamping subtracter, the second polar plate of the capacitor and the second end of the transistor are grounded, the output end of the time comparator is connected with the first input end of the AND gate, the enabling signal is connected with the second input end of the AND gate through the inverter, and the output end of the AND gate is connected with the setting end of the RS trigger; The reset end of the RS trigger and the reset end of the fifth D trigger are connected with the output end of the phase-dislocation delay device, the normal phase output end of the RS trigger is connected with the enabling end of the clock circuit of other channels and the reset end of the clock selection circuit, the clock end of the fifth D trigger is connected with the control output end of the clock selection circuit, the input end of the fifth D trigger is connected with the power supply voltage, and the reverse phase output end of the fifth D trigger is connected with the control end of the transistor.
8. A multi-channel voltage converter comprising the clock circuit of any one of claims 1-7.
9. A power management chip comprising the multi-channel voltage converter of claim 8.

Description

Multi-channel voltage converter, clock circuit thereof and power management chip Technical Field Embodiments of the present disclosure relate to the field of integrated circuits, and in particular, to a multi-channel voltage converter, a clock circuit thereof, and a power management chip. Background A Power management chip (PMIC) is a common analog chip, and its main function is to provide Power management functions for various electronic devices, and is responsible for managing Power supply of the various chips on a Circuit board of an electronic product, and generally includes a multi-channel Direct Current (DC) -DC converter and/or a multi-channel low dropout linear regulator (Low Dropout Regulator, LDO). For a PMIC comprising a multi-channel DC-DC converter, the channel clock signal of each channel DC-DC converter in a continuous conduction mode is generated by a reference clock module to a reference clock signal in a misphase mode, and the channel clock signal of the corresponding channel DC-DC converter in a discontinuous conduction mode is generated by a channel clock module of the corresponding channel DC-DC converter, wherein the channel clock module generates a clock signal with a frequency lower than the frequency of the reference clock signal so as to maintain the normal output of the corresponding channel DC-DC converter in a light load state. By adopting the technical scheme, each channel DC-DC converter can work in a wrong phase in a continuous conduction mode, however, in a discontinuous conduction mode, the internal clock modules of each channel DC-DC converter are completely independent, so that the wrong phase work of each channel DC-DC converter cannot be ensured. Disclosure of Invention The disclosure provides a multi-channel voltage converter, a clock circuit thereof and a power management chip, which can ensure that each channel in the multi-channel voltage converter works in a phase-shifting manner in a discontinuous conduction mode. In a first aspect, the present disclosure provides a clock circuit of a multi-channel voltage converter, including a reference clock circuit and N channel clock circuits, N output ends of the reference clock circuit are connected in one-to-one correspondence with N input ends of each channel clock circuit, and N is an integer greater than or equal to 2. The reference clock circuit is configured to generate a reference clock signal and perform a phase-shifting process on the reference clock signal to obtain N sub-clock signals. And when the channel working mode is a discontinuous conduction mode, determining a channel target sub-clock signal of a next period at a channel delay time after the channel target sub-clock signal of a current period is ended, generating a channel clock signal of the next period based on the channel target sub-clock signal of the next period, and controlling other channel clock circuits to be disabled within the phase-dislocation delay time after the channel target sub-clock signal enters the next period. And in each period, the channel clock signal is aligned with the rising edge of the channel target sub-clock signal, and the channel target sub-clock signal in the next period is the signal with the nearest rising edge of the N sub-clock signals from the channel delay time after the current period is ended. In some embodiments of the disclosure, each channel clock circuit includes a clock selection circuit and a mode detection circuit, N input terminals of the clock selection circuit are connected in one-to-one correspondence with N output terminals of the reference clock circuit, a first input terminal of the mode detection circuit is connected to the channel load detection voltage, a second input terminal of the mode detection circuit is connected to the detection reference voltage, and an output terminal of the mode detection circuit is connected to a control terminal of the clock selection circuit. The mode detection circuit is configured to determine a channel mode detection signal based on whether the channel load detection voltage is greater than the detection reference voltage. The clock selection circuit is configured to select one of the N sub-clock signals as the channel target sub-clock signal when the channel mode detection signal is a continuous conduction mode signal, and determine that the channel target sub-clock signal in a continuous conduction mode is the channel target sub-clock signal of a first period in the discontinuous conduction mode when the channel mode detection signal is a discontinuous conduction mode signal, and flip a channel delay time signal to be a sub-clock signal which reaches first rising edges of the N sub-clock signals after invalidation is determined as the channel target sub-clock signal of the next period in the current period of the discontinuous conduction mode. In some embodiments of the disclosure, each channel clock circuit further includes a clock determination circuit, an input