CN-121602959-B - Low-mismatch ultra-wideband active balun

Abstract

The invention discloses a low-mismatch ultra-wideband active balun, which belongs to the technical field of analog integrated circuits and comprises a first-stage amplifier and a second-stage amplifier which are sequentially arranged. The first-stage amplifier adopts a differential structure, and finally realizes the conversion from a single-ended signal to a differential signal with constant amplitude and opposite phase. The second-stage amplifier isolates the influence of the load of the later stage on the earlier stage, and ensures the symmetry of the differential signal. In the second-stage amplifier, the seventh NMOS transistor and the tenth NMOS transistor form positive feedback, the gate-source voltage difference of the eighth NMOS transistor and the ninth NMOS transistor is increased by introducing a cross coupling capacitor to form voltage recovery, and compared with the traditional active balun, the second-stage amplifier reduces the phase and amplitude mismatch of an output signal through positive feedback, simultaneously expands the bandwidth, increases the gate-source signal amplitude by utilizing the source voltage recovery, enhances the equivalent transconductance, and further stabilizes the phase and amplitude of the output signal.

Inventors

• LI ZHEN
• ZHANG XUANYING
• Duan Shize
• CUI YUANYUAN
• ZHAO XIAODONG

Assignees

• 西北工业大学

Dates

Publication Date

20260512

Application Date

20260128

Claims (3)

1. 1. The low-mismatch ultra-wideband active balun is characterized by comprising a first-stage amplifier and a second-stage amplifier which are sequentially arranged; the first-stage amplifier adopts a differential pair structure to realize the conversion from a single-ended signal to a differential signal with constant amplitude and opposite phase, and eliminates an unbalanced signal transmitted by a common mode, thereby obtaining a balanced output signal; The second-stage amplifier adopts a positive feedback structure and a voltage recovery structure, wherein the positive feedback structure is used for reducing the phase and amplitude mismatch of balanced output signals and expanding bandwidth at the same time, the voltage recovery structure is used for increasing the amplitude of input signals received by the second-stage amplifier, so that the transconductance is equivalently improved, the phase and the amplitude of the output signals are further stabilized to realize the amplitude-phase balance, and amplified signals are output; The voltage recovery structure includes: An eighth NMOS transistor M 8 , a ninth NMOS transistor M 9 , a first capacitor C 1 , and a second capacitor C 2 ; The voltage recycling structure couples the voltage of the opposite side output node to the gates of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9 through the first capacitor C 1 and the second capacitor C 2 , and enhances the amplitude of the gate-source voltage of the internal transistor itself, so as to enhance the equivalent transconductance of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9 , and at the same time counteract the gate-source parasitic capacitance of the internal transistor at high frequency; In the voltage recycling structure, the first capacitor C 1 and the second capacitor C 2 form a cross-coupling capacitor, the amplitude of the gate-source voltages of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9 is increased by introducing the cross-coupling capacitor, and under the condition that the transconductance of the eighth NMOS transistor and the ninth NMOS transistor is unchanged, current multiplication is realized, and meanwhile, the gate-source parasitic capacitance of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9 is counteracted at high frequency; The source of the seventh NMOS transistor M 7 is respectively connected with the source of the eighth NMOS transistor M 8 and the first end of the first capacitor C 1 , the grid is respectively connected with the drain of the ninth NMOS transistor M 9 and the drain of the tenth NMOS transistor M 10 , and the drain is respectively connected with the drain of the eighth NMOS transistor M 8 and the grid of the tenth NMOS transistor M 10 ; The source of the tenth NMOS transistor M 10 is connected to the source of the ninth NMOS transistor M 9 and the first end of the second capacitor C 2 , respectively.
2. 2. A low mismatch ultra wideband active balun according to claim 1, wherein said first stage amplifier comprises: The first NMOS transistor M 1 , the second NMOS transistor M 2 , the third NMOS transistor M 3 , the first resistor R 1 and the second resistor R 2 ; The source electrode of the first NMOS transistor M 1 is connected with the drain electrode of the third NMOS transistor M 3 , the grid electrode is connected with an input signal, and the drain electrode of the second NMOS transistor M 2 serve as differential output ends of the first-stage amplifier; The source electrode of the second NMOS transistor M 2 is connected with the drain electrode of the third NMOS transistor M 3 , and the grid electrode is grounded; The source electrode of the third NMOS transistor M 3 is grounded, and the grid electrode is connected with a fixed voltage V B ; A first end of the first resistor R 1 is connected with a power supply voltage, and a second end of the first resistor R 1 is connected with a drain electrode of the first NMOS transistor M 1 ; The first end of the second resistor R 2 is connected to the power supply voltage, and the second end is connected to the drain of the second NMOS transistor M 2 .
3. 3. A low mismatch ultra wideband active balun according to claim 1, wherein said second stage amplifier comprises: The fourth NMOS transistor M 4 , the fifth NMOS transistor M 5 , the sixth NMOS transistor M 6 , the seventh NMOS transistor M 7 , the eighth NMOS transistor M 8 , the ninth NMOS transistor M 9 , the tenth NMOS transistor M 10 , the third resistor R 3 , the fourth resistor R 4 , the fifth resistor R 5 , the sixth resistor R 6 , the first capacitor C 1 , and the second capacitor C 2 ; The source electrode of the fourth NMOS transistor M 4 is grounded, the grid electrode is connected with a fixed voltage V B , and the drain electrode is connected with the source electrode of the fifth NMOS transistor M 5 ; The source of the fifth NMOS transistor M 5 is connected to the source of the sixth NMOS transistor M 6 , the gate of the fifth NMOS transistor M 5 and the gate of the sixth NMOS transistor M 6 are used as differential input terminals of the second stage amplifier, and the drain of the fifth NMOS transistor M 5 and the source of the eighth NMOS transistor M 8 are respectively connected to the source of the seventh NMOS transistor M 7 and the source of the eighth NMOS transistor M 8 , and the first end of the first capacitor C 1 ; The drain electrode of the sixth NMOS transistor M 6 is connected to the source electrode of the ninth NMOS transistor M 9 , the source electrode of the tenth NMOS transistor M 10 , and the first end of the second capacitor C 2 , respectively; The gate of the seventh NMOS transistor M 7 and the gate of the tenth NMOS transistor M 10 are used as differential output ends of the second-stage amplifier, the gate of the seventh NMOS transistor M 7 is respectively connected to the drain of the ninth NMOS transistor M 9 , the drain of the tenth NMOS transistor M 10 , and the first end of the fourth resistor R 4 , and the drain is respectively connected to the drain of the eighth NMOS transistor M 8 , the gate of the tenth NMOS transistor M 10 , and the first end of the third resistor R 3 ; the gate of the eighth NMOS transistor M 8 is connected to the first end of the fifth resistor R 5 and the second end of the second capacitor C 2 , respectively; The gate of the ninth NMOS transistor M 9 is connected to the first end of the sixth resistor R 6 and the second end of the first capacitor C 1 , respectively; The second end of the third resistor R 3 is connected to a power supply voltage; the second end of the fourth resistor R 4 is connected to a power supply voltage; The second end of the fifth resistor R 5 is connected to the second end of the sixth resistor R 6 , and is connected to the fixed voltage V B .

Description

Low-mismatch ultra-wideband active balun Technical Field The invention belongs to the technical field of analog integrated circuits, and particularly relates to a low-mismatch ultra-wideband active balun. Background In a radio frequency transceiver system, a receiving end is one of key modules. But signal transmitters typically emit single ended signals. In order to eliminate glitches and interference in the signal to enhance the control of the system on the common mode signal, the receiving end is often implemented in a differential form. Compared with a single-ended circuit, the differential circuit can improve the working bandwidth, the common mode rejection ratio, the even harmonic distortion and the anti-interference capability of signals. The balun circuit can realize the conversion of the radio frequency signal from single end to differential, and simultaneously provide certain gain, linearity and better reverse isolation for the system. The balun is passive and active, and has certain insertion loss due to non-ideal factors such as parasitic resistance, capacitance, dielectric loss, electromagnetic loss and the like, and the low-frequency passive balun has large area, is unfavorable for system integration, and increases application cost. The active balun is realized based on a transistor active amplifier, has small occupied area, is convenient for on-chip integration, can provide a certain gain while converting signals, and is easier to realize broadband and impedance matching. In the existing active balun design, in order to compensate high-frequency gain and inhibit amplitude and phase errors of an output end, a Chinese patent with a publication number of CN114938206A adopts an inductor to perform phase and gain compensation. However, this approach results in a significant increase in circuit area, not only reduces chip integration, increases manufacturing cost, but also causes high frequency performance degradation due to inductive parasitics, and is too sensitive to process variations. The scheme severely restricts the urgent need of the modern high-speed wireless communication system for compact and high-reliability balun circuits. Therefore, how to expand the active balun working bandwidth while keeping smaller phase error and gain error becomes a problem to be solved urgently. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a low-mismatch ultra-wideband active balun. The technical problems to be solved by the invention are realized by the following technical scheme: The invention provides a low-mismatch ultra-wideband active balun, which comprises a first-stage amplifier and a second-stage amplifier which are sequentially arranged; the first-stage amplifier adopts a differential pair structure to realize the conversion from a single-ended signal to a differential signal with constant amplitude and opposite phase, and eliminates an unbalanced signal transmitted by a common mode, thereby obtaining a balanced output signal; The second-stage amplifier adopts a positive feedback structure and a voltage recovery structure, reduces the phase and amplitude mismatch of balanced output signals and simultaneously expands the bandwidth by utilizing the positive feedback structure, increases the amplitude of input signals received by the second-stage amplifier by utilizing the voltage recovery structure, equivalently improves the transconductance, further stabilizes the phase and the amplitude of the output signals to realize the amplitude-phase balance, and outputs amplified signals; The voltage recovery structure includes: An eighth NMOS transistor M 8, a ninth NMOS transistor M 9, a first capacitor C 1, and a second capacitor C 2; The voltage recycling structure couples the voltage of the opposite side output node to the gates of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9 through the first capacitor C 1 and the second capacitor C 2, and enhances the amplitude of the gate-source voltage of the internal transistor itself, so as to enhance the equivalent transconductance of the eighth NMOS transistor M 8 and the ninth NMOS transistor M 9, and at the same time, cancel the gate-source parasitic capacitance of the internal transistor at high frequency. The invention has the beneficial effects that: In the scheme provided by the invention, the low-mismatch ultra-wideband active balun adopts a two-stage structure to increase isolation, reduce the influence of a rear-stage load on a front stage, and the first-stage amplifier adopts a differential structure, has excellent common-mode rejection ratio and good output matching property, and the second-stage amplifier reduces the mismatch of phase and amplitude through positive feedback, thereby completing amplitude-phase balance, and in addition, the positive feedback improves the working speed of the second-stage amplifier, thereby improving the bandwidth. Furthermore, the invention increases th