CN-121604472-B - Planar SiC MOSFET device structure and manufacturing method thereof

CN121604472BCN 121604472 BCN121604472 BCN 121604472BCN-121604472-B

Abstract

The invention relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof, wherein the device structure comprises a substrate, an epitaxial layer positioned on the substrate, a doping area and a JFET area positioned on the epitaxial layer, wherein the substrate is a silicon carbide SiC substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is positioned between the doping regions and is in contact with the doping regions, the upper surface of the JFET region, the upper surface of the doping regions and the upper surface of the epitaxial layer are positioned on the same set surface, the set surface is a concave surface, the concave portion of the concave surface covers the JFET region and the designated region of the doping regions, and the designated region is a region at least comprising a channel of the doping regions. Through the device structure, on the premise of guaranteeing the performances of other devices except on-resistance, the on-electrons of the device are effectively reduced.

Inventors

Cai Zhengkun
LIAO GUANGCHAO
ZHANG WEI
TIAN TIAN

Assignees

深圳云潼微电子科技有限公司
重庆云潼科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260130

Claims (8)

1. The planar SiC MOSFET device structure is characterized by comprising a substrate, an epitaxial layer positioned on the substrate, a doped region and a JFET region positioned on the epitaxial layer, wherein the substrate is a silicon carbide SiC substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is positioned between the doping regions, and the JFET region is contacted with the doping regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are positioned on the same setting surface, and the setting surface is a concave surface; The concave part covers the appointed area of the JFET region and the doping region so as to reduce the on-resistance of the device structure through the concave surface and the concave part, wherein the appointed area is an area at least comprising a channel of the doping region; the angle of the concave part is 1-4 degrees, so that the current density of a channel, an accumulation layer and a JFET region below a grid electrode is increased, the interface state density can be reduced, the carrier mobility of the surface is improved, the tensile stress is introduced, the scattering is reduced, the effective quality of electrons is reduced, and the mobility is further improved; the depth range of the concave part is 0.05 um-0.2 um, and the concave part is a flat curved surface.
2. The planar SiC MOSFET device structure of claim 1, wherein a maximum opening width of the recess is no less than a sum of a width of the JFET region and a channel width in the doped region.
3. The planar SiC MOSFET device structure of claim 2, wherein a mask during fabrication of the recess is the same mask as a mask during fabrication of the JFET region.
4. The planar SiC MOSFET device structure of any one of claims 1-3, wherein said doped region comprises a P-type well region, an n+ region, and a p+ region; the N+ region and the P+ region are positioned in the P-type well region, and the upper surface of the N+ region, the upper surface of the P+ region and the upper surface of the P-type well region are positioned on the same setting surface; one side of the N+ region is close to the JFET region, and the other side of the N+ region is in contact with the P+ region.
5. The planar SiC MOSFET device structure as recited in claim 4 further comprising a gate region over said epitaxial layer, said gate region overlying a portion of said JFET region and said doped region; The grid electrode region comprises a grid electrode dielectric layer and grid electrode polysilicon; The grid dielectric layer is positioned on the epitaxial layer and covers the JFET region and a partial region of the doping region; The gate polysilicon is located over the gate dielectric layer.
6. The planar SiC MOSFET device structure as recited in claim 5 further comprising an interlayer dielectric layer overlying said epitaxial layer and surrounding said gate region.
7. The planar SiC MOSFET device structure as recited in claim 6 further comprising a source metal layer and a drain metal layer; The source electrode metal layer is positioned on the epitaxial layer and covers the interlayer dielectric layer, the gate region and the doped region; the drain metal layer is located under the substrate.
8. A method of fabricating a planar SiC MOSFET device structure according to any one of claims 1-7, the method comprising: forming an epitaxial layer on a substrate, wherein the substrate is a silicon carbide (SiC) substrate, and the epitaxial layer is a SiC epitaxial layer; And forming a doped region and a JFET region on the epitaxial layer, wherein the JFET region is positioned between the doped regions and is in contact with the doped region, the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are positioned on the same set surface, the set surface is a concave surface, the concave part of the concave surface covers the JFET region and a designated area of the doped region, so that the on-resistance of a device structure is reduced through the concave surface and the concave part, and the designated area is an area at least comprising a channel of the doped region.

Description

Planar SiC MOSFET device structure and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a planar SiC MOSFET device structure and a manufacturing method thereof. Background The SiC MOSFET device has great potential in application fields such as high voltage, high temperature, high frequency and the like due to a series of outstanding advantages such as large forbidden bandwidth, high critical breakdown electric field, high electron saturation drift speed, high heat conductivity and the like, and particularly in fields such as new energy automobiles, photovoltaic energy storage, charging piles and the like which are emerging in recent years. Because of the process technology and machine limitations, the domestic wafer factories mostly adopt planar gate silicon carbide (SiC MOSFET) device structures. Compared with the trench gate SiC MOSFET device structure, the planar gate SiC MOSFET device structure has the advantages of lower manufacturing difficulty, higher device product yield, no high electric field concentration problem of the trench gate SiC MOSFET device structure, and more excellent avalanche resistance. However, due to the rough surface of the planar gate SiC MOSFET, mobility is low, and the problems of large JFET region and cell size and the like exist in the SiC MOSFET device structure, the on-resistance and parasitic capacitance of the SiC MOSFET device are larger compared with those of the trench gate SiC MOSFET device. Especially, the key parameter of on-resistance affects the product cost and practical application of the device, and is the pain point problem of the current planar gate SiC MOSFET device. In order to solve the pain point problem, the existing methods for reducing the on-resistance of the SiC MOSFET device include the following methods: 1. the doping concentration of the JFET region of the device is optimized, the purpose of reducing the JFET resistance is achieved, and the effect of reducing the on-resistance of the device is achieved. When the doping concentration of the JFET region is increased to a certain degree, the drain-source leakage current of the device is obviously increased, and the reliability of gate oxide is greatly reduced. 2. The channel length of the device is reduced, and the channel resistance occupying higher on-resistance is reduced. When the channel length is reduced to a certain degree, the method can cause short channel effect and is easy to cause drain-source punch-through. 3. The cell size of the device is reduced, the channel density is increased, and the channel resistance and the JFET resistance are reduced. When the cell size is reduced to a certain extent, the yield is greatly reduced due to the limitation of the machine, and the increase of the resistance of the JFET region also counteracts the benefit brought by the reduction of the cell size. Although the conventional SiC MOSFET device can reduce the on-resistance to a certain extent, after the structure for reducing the on-resistance is optimized to a certain extent, the benefit of the conventional SiC MOSFET device is obviously reduced, and other device parameters are seriously affected. Therefore, the conventional SiC MOSFET device has a problem of reducing on-resistance while affecting other device parameters other than on-resistance. ‌ A Disclosure of Invention The embodiment of the application solves the technical problems of reducing the on-resistance and influencing other device parameters except the on-resistance in the prior art by providing the planar SiC MOSFET device structure and the manufacturing method thereof, and effectively reduces the technical effects of conducting electrons and the like of the device on the premise of ensuring the performances of other devices except the on-resistance. In a first aspect, an embodiment of the present invention provides a planar SiC MOSFET device structure, including a substrate, an epitaxial layer located above the substrate, a doped region located on the epitaxial layer, and a JFET region, where the substrate is a silicon carbide SiC substrate, and the epitaxial layer is a SiC epitaxial layer; the JFET region is positioned between the doping regions, and the JFET region is contacted with the doping regions; the upper surface of the JFET region, the upper surface of the doped region and the upper surface of the epitaxial layer are positioned on the same setting surface, and the setting surface is a concave surface; The concave recess covers the JFET region and a designated area of the doped region, so that the on-resistance of the device structure is reduced through the concave recess and the concave recess, wherein the designated area is an area at least comprising a channel of the doped region. Optionally, the angle of the concave part is 1-4 degrees. Optionally, the depth range of the concave part is 0.05 um-0.2 um. Optionally, the maximum opening width of the r