CN-121614182-B - Multithreading instruction fetching scheduling system

CN121614182BCN 121614182 BCN121614182 BCN 121614182BCN-121614182-B

Abstract

The invention provides a multithread instruction fetching scheduling system, which relates to the technical field of computer architecture and comprises a thread dynamic scheduling module, wherein the thread dynamic scheduling module can dynamically update the priority of threads according to the polling count and the waiting time of the threads, so that each thread can obtain scheduling opportunities in the instruction fetching process, the problem that the threads with low priority cannot be starved for a long time in the traditional fixed priority mode are solved, the scheduling fairness is improved, and meanwhile, when a certain thread has cache miss, the buffer management module provided by the invention can suspend the instruction fetching request corresponding to the thread, and scheduling logic can be immediately switched to other threads to continue instruction fetching, thereby avoiding that a single thread blocks the whole front-end assembly line, and remarkably improving the overall instruction fetching efficiency, throughput rate and effective instruction fetching bandwidth of the system.

Inventors

ZHANG XUANYING
CUI YUANYUAN
ZHAO XIAODONG
ZHANG HAIJIN
LI JIAQING

Assignees

西北工业大学

Dates

Publication Date: 20260505
Application Date: 20260202

Claims (8)

1. A multi-threaded finger dispatch system, comprising: The storage control module is used for receiving, storing and executing the instruction fetching request, judging whether the instruction fetching request hits the instruction cache or not, and receiving data corresponding to the first instruction fetching request returned by the instruction cache when the first instruction fetching request hits the instruction cache, and transmitting the data to the instruction fetching unit; The buffer area management module is used for receiving and managing the second instruction fetch request when the second instruction fetch request misses the instruction cache; When the external bus returns the first data corresponding to the second instruction fetch request, the buffer management module feeds back a return result to the storage control module, and the storage control module writes the first data back to the corresponding instruction fetch channel according to the return result, and simultaneously updates the state of the thread corresponding to the second instruction fetch request into an attractive state; The system comprises a thread dynamic scheduling module, a storage control module, a first thread processing module and a second thread processing module, wherein the thread dynamic scheduling module is used for updating the priority of a first thread according to the polling count and the waiting time of the first thread in each scheduling period, generating scheduling results based on the priorities of a plurality of first threads when each scheduling period is finished, and transmitting the scheduling results to the storage control module, wherein the first thread is a thread in a removable finger state corresponding to a finger request in the storage control module; the method comprises the steps of allocating a priority register unit for each thread to record the current value of the priority of the thread, setting the priority register unit of each thread to be the same initial value when a system is initialized, receiving state information of each thread by a thread dynamic scheduling module when each scheduling period starts, wherein the state information comprises a thread identifier, whether the state information is in a desirable instruction state, whether the state information is in a cache miss waiting state and the waiting time and the polling times corresponding to the thread, and updating the priority of each thread by the thread dynamic scheduling module based on the state information of each thread; the updating of the priority of each thread based on the state information of each thread includes: if a thread is in a waiting state of a buffer zone, the corresponding priority is kept unchanged or attenuated and does not participate in the scheduling of the current scheduling period, if the thread is in a removable instruction state and is not selected in the last scheduling period, the waiting time of the thread is self-increased, the value of the corresponding priority is increased according to a preset value, and if the thread is selected to execute instruction taking in the current period, the value of the corresponding priority is restored to the initial value.
2. The multithreaded finger dispatch system of claim 1, wherein the memory control module comprises a thread identification register module and a multi-source instruction memory arbitration module; the thread identification register module is used for adding a thread identification for the instruction fetch request when the instruction fetch request enters the instruction fetch unit, and the thread identification is stored in the hardware register and used for indicating the thread to which the instruction fetch request belongs; The multi-source instruction storage arbitration module is used for receiving the instruction fetch request, judging the address range based on the instruction fetch address corresponding to the instruction fetch request, and judging whether the instruction fetch request hits the instruction cache or not if the address range of the instruction fetch request falls into the address range corresponding to the instruction cache; When a plurality of threads initiate a fetching request at the same time, the multi-source instruction storage arbitration module determines a target thread in the current dispatching cycle according to the dispatching result output by the thread dynamic dispatching module of the previous dispatching cycle, and executes the fetching request corresponding to the target thread, wherein the dispatching result comprises a first thread identifier of the target thread, and the first thread identifier is used for indicating the multi-source instruction storage arbitration module to select a fetching path of the fetching request corresponding to the first thread identifier.
3. The multi-threaded instruction fetch scheduling system of claim 2, wherein the multi-source instruction store arbitration module connects an instruction cache, an instruction tightly coupled memory, and a bypass path; When the multi-source instruction storage arbitration module executes the instruction fetch request, if the instruction fetch address corresponding to the instruction fetch request falls into the address interval corresponding to the instruction close-coupled memory, the instruction fetch request is routed to the instruction close-coupled memory, if the instruction fetch address corresponding to the instruction fetch request falls into the address interval corresponding to the instruction cache, the judgment of whether the instruction fetch request hits the instruction cache is carried out, if the instruction fetch address corresponding to the instruction fetch request falls into the address interval corresponding to the bypass path, the instruction fetch request initiates bus access through the bypass path, and after data is returned by the main memory or the peripheral, the multi-source instruction storage arbitration module feeds back the thread corresponding to the instruction fetch request.
4. The multithreaded instruction fetch scheduling system of claim 2, wherein after updating the priorities of all threads, a second thread identifier is transmitted to the multi-source instruction storage arbitration module, where the second thread identifier is the thread identifier corresponding to the thread with the highest priority.
5. The multi-threaded finger dispatch system of claim 1, wherein the updating of the priority of each thread based on the state information of each thread further comprises: if the waiting time of a thread exceeds a preset waiting time threshold value, the corresponding value of the priority is increased.
6. The multi-threaded fetch scheduling system of claim 2, wherein after the buffer management module receives the second fetch request, the buffer management module generates a record based on the second fetch request and stores the record, wherein the record includes the thread identifier, the fetch address, the access type and the current state information corresponding to the second fetch request, one of the second fetch requests corresponds to one of the records, and the record is used for parallel queuing of the second fetch requests corresponding to different threads; When the bus returns the data required by the second instruction fetch request, the buffer management module feeds back the returned result corresponding to the second instruction fetch request and the thread identifier to the multi-source instruction storage arbitration module together, so that the multi-source instruction storage arbitration module resumes instruction fetch execution of the thread corresponding to the second instruction fetch request.
7. The multi-threaded finger dispatch system of claim 3, further comprising an error detection and isolation module; During fetching, the error detection and isolation module performs parity checking or error detection and correction detection on data from the instruction tightly coupled memory and the instruction cache.
8. The multi-threaded instruction fetch scheduling system of claim 7, wherein if the error detection and isolation module detects that the second data has a single-bit error, the second data is corrected online and the corrected second data is rewritten to be stored, and if the third data has a multi-bit error, only the instruction fetch request of the thread corresponding to the third data is blocked and the system is notified through an exception mechanism.

Description

Multithreading instruction fetching scheduling system Technical Field The invention relates to the technical field of computer architecture, in particular to a multithreading instruction fetching scheduling system. Background With the widespread use of multithreading in processors, multiple hardware threads may be executed in parallel to improve instruction level parallelism and system throughput. In a multithreaded processor, the front-end fetch unit and instruction storage structures (e.g., instruction cache ICAChe, instruction tightly coupled memory ICCM, etc.) are typically shared by multiple threads. Fetch requests issued by different threads need to be arbitrated and scheduled under limited cache ports and storage bandwidth resources. In the prior art, the multithreading instruction fetching scheduling mainly adopts a fixed priority scheduling mode, wherein the threads fetch according to a preset fixed priority. When the high priority thread is continuously active, the low priority thread may not obtain the instruction taking opportunity for a long time, which easily causes thread starvation and the whole fairness of the system is insufficient. And secondly, a polling scheduling mode, wherein a scheduler allocates finger taking opportunities to each thread in turn according to the sequence. Although fairness among threads can be guaranteed to a certain extent, when a certain thread has a cache miss (miss) and enters a waiting state, polling scheduling may still continue to allocate a finger taking time slot for the thread, so that invalid scheduling is caused, and effective finger taking bandwidth is reduced. In addition, in some architectures, if a cache miss occurs in a fetch request of a certain thread, the whole front-end fetch unit is blocked, and even if executable fetch requests still exist in other threads, the response cannot be timely obtained. This global blocking mechanism significantly reduces the throughput of the multi-threaded system. Meanwhile, in the prior art, although a parity check or partial error detection mechanism is introduced in the process of accessing an instruction cache, when an error occurs, the whole cache is always required to be refreshed or the whole instruction fetching process is suspended, and independent isolation and fine granularity restoration capability of single-thread instruction fetching requests are lacked. Therefore, there is still a need for improvement in the fairness and effective bandwidth utilization of the scheduling mechanisms of the multi-threaded instruction fetch scheduling system in the prior art. Disclosure of Invention The present invention is directed to a multi-threaded finger dispatch system to improve the above-mentioned problems. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: The application provides a multithreading instruction fetching scheduling system, which comprises the following steps: The storage control module is used for receiving, storing and executing the instruction fetching request, judging whether the instruction fetching request hits the instruction cache or not, and receiving data corresponding to the first instruction fetching request returned by the instruction cache when the first instruction fetching request hits the instruction cache, and transmitting the data to the instruction fetching unit; The buffer area management module is used for receiving and managing the second instruction fetch request when the second instruction fetch request misses the instruction cache; When the external bus returns the first data corresponding to the second instruction fetch request, the buffer management module feeds back a return result to the storage control module, and the storage control module writes the first data back to the corresponding instruction fetch channel according to the return result, and simultaneously updates the state of the thread corresponding to the second instruction fetch request into an attractive state; The thread dynamic scheduling module is used for updating the priority of a first thread according to the polling count and the waiting time of the first thread in each scheduling period, generating scheduling results based on the priorities of a plurality of first threads when each scheduling period is finished, and transmitting the scheduling results to the storage control module, wherein the first thread is a thread in a removable finger state corresponding to a finger fetching request in the storage control module; And after receiving the scheduling result, the storage control module executes a second thread based on the scheduling result. As a preferable scheme of the invention, the storage control module comprises a thread identification registering module and a multi-source instruction storage arbitration module; the thread identification register module is used for adding a thread identification for the instruction fetch request when the instru