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CN-121614277-B - Memory real-time enhancement method based on Preempt _RT

CN121614277BCN 121614277 BCN121614277 BCN 121614277BCN-121614277-B

Abstract

The invention discloses a Preempt-RT-based memory instantaneity enhancing method, which comprises the following steps of S1, constructing a user-state memory pool without page missing abnormality, adjusting a kernel starting parameter memmap, reserving a continuous physical address, downloading jemalloc source codes, modifying configuration, writing an LD_PRELOAD shared library, and replacing an application memory allocation library through the LD_PRELOAD in a non-sense mode, S2, deploying and configuring a Cache Color, namely configuring MPAM for a designated CPU, creating MPAM partitions, configuring MPAM resource quota, binding a target application to the designated CPU and MPAM partitions, S3, optimizing system configuration, namely disabling swap, closing ASLR, giving special permission to the target application, optimizing kswapd background recovery parameters, and closing transparent large page background merging.

Inventors

  • GUO HAO
  • WU CHUNGUANG
  • LIU GUISHAN
  • TAO SHUSONG
  • WU YAOWEI

Assignees

  • 麒麟软件有限公司

Dates

Publication Date
20260508
Application Date
20260202

Claims (10)

  1. 1. A memory real-time enhancement method based on Preempt _RT is characterized in that a deterministic memory management system is constructed through a multi-cooperation method of hardware isolation, memory reservation, user state management and system optimization, so that the memory real-time enhancement is realized, wherein the memory reservation and the user state management are realized through a step S1, the hardware isolation is realized through a step S2, and the system optimization is realized through a step S3; Step S1, a user state memory pool without page fault is constructed, namely, a kernel starting parameter memmap is adjusted, a continuous physical address is reserved, jemalloc source codes are downloaded, configuration is modified, an LD_PRELOAD shared library is written, and a memory allocation library is applied through LD_PRELOAD non-inductive replacement, so that a user state memory pool management mechanism is realized, memory allocation page fault is eliminated, and memory competition and fragmentation interference are avoided; Step S2, deploying and configuring a Cache Color, namely configuring MPAM for a designated CPU, creating MPAM partition and configuring MPAM resource quota, binding a target application to the designated CPU and MPAM partition, and improving the resource exclusivity and delay certainty of a core real-time task; And S3, system configuration optimization, namely, disabling the swap, closing the ASLR, giving special permission to the target application, optimizing kswapd background recovery parameters, closing transparent large page background merging, eliminating bottom layer interference, and compressing unpredictable overhead caused by background processes.
  2. 2. The method of claim 1 wherein downloading jemalloc source code and modifying configuration includes disabling mmap and brk, turning on thread local cache, turning off background reclamation and memory statistics, and compiling jemalloc into dynamic library libjelloc.
  3. 3. The method of claim 2 wherein writing the LD_PRELOAD shared library comprises using mmap to map the starting address memory, binding jemalloc memory allocation and release functions to the mapped starting address memory region, re-writing multiple function volumes, and compiling into the rt_ jemalloc _hook.
  4. 4. The method for enhancing memory instantaneity based on Preempt _rt according to claim 1, wherein configuring MPAM for the specified CPU in step S2 includes the steps of: step S211, isolating the CPU0 through grub configuration, and prohibiting the system default task from being scheduled to the core; Step S212, adding mpam.part id_base=100 to the kernel start parameter, that is, setting a start ID for MPAM partitions.
  5. 5. The method for memory instantaneity enhancement based on Preempt _rt of claim 1, wherein creating MPAM the partition comprises the steps of: step S221, creating an rt_cpu0_ mpam folder in the/sys/fs/cgroup folder, and creating a cgroup V2 partition for the appointed CPU; Step S222, limiting the partition to only use the isolated CPU0; Step S223, writing "+ mpam +cache+memory.bandwidth" into the rt_cpu0_ mpam file to enable MPAM, cache and bandwidth control.
  6. 6. The method of claim 4 wherein optimizing kswapd background reclamation parameters includes binding kswapd to cores other than CPU0, limiting kswapd reclamation speed, fixing kswapd wake threshold and not actively reclaiming anonymous pages.
  7. 7. The method of claim 6, wherein 64 is written to per proc/sys/vm/pageout io blocks to limit kswapd recovery rate.
  8. 8. The method of claim 6, wherein 1 is written to/proc/sys/vm/watermark_scale_factor to fix the wake-up threshold of kswapd.
  9. 9. The method of claim 6, wherein 0 is written to/proc/sys/vm/swappiness to not actively reclaim anonymous pages.
  10. 10. The method of claim 1, wherein a new is written to/sys/kernel/mm/transparent_ hugepage/khugepaged/defrag to disable transparent large page background merging.

Description

Memory real-time enhancement method based on Preempt _RT Technical Field The invention relates to the technical field of operating systems, in particular to a Preempt _RT-based memory instantaneity enhancing method. Background The uncertainty of Linux kernel memory management is contradictory with the requirements of industrial control scenes on control cycle stability, instruction response timeliness and motion axis synchronization precision due to design logic of dynamic on-demand distribution, global lock synchronization and background asynchronous optimization, so that the uncertainty of industrial core scenes such as PLC logic control, motion control and sensor data real-time processing is caused, and the method is specifically expressed as follows: The memory allocation link, the partner system needs to dynamically merge and fragment the idle pages, the merging times and the time consumption fluctuate along with the fragmentation degree of the system memory, and the execution precision of a PLC periodic task (such as a 1ms scanning period) is directly influenced, so that control deviation is caused; In an address translation link, the probability and the processing time consumption of the TLB Miss cannot be predicted due to the interference of a memory access mode and an address space randomization (ASLR) of an industrial task (such as high-frequency IO data interaction), context switching or page table modification triggering TLB refreshing operation is needed to synchronize the states of the multi-core TLB, and under the multi-core architecture of an industrial controller, the synchronization delay is prolonged along with the increase of the number of cores, so that the synchronization precision of multi-axis linkage is destroyed; The CPU cache interaction link, the cache conflict caused by group association mapping, pseudo sharing caused by multi-core sharing industrial control data and dynamic selection of a cache replacement strategy can cause uncontrollable time and frequency of cache invalidation, thereby causing time-consuming fluctuation of control instruction execution and influencing real-time response of servo drive; The uncertainty of a memory recycling mechanism is particularly remarkable for industrial control threat, wherein the awakening time of a background recycling thread kswapd is determined by a vm.min_free_kbytes threshold value and industrial field real-time load (such as batch data uploading and multi-equipment concurrent access), and the scanning range and page cleaning time of the recycling process are not fixed, so that the direct memory recycling can block the current control task, the time consumption is dependent on the number of recyclable pages and the lock competition strength, and if the recycling partition page swap-in and swap-out is related, completely unpredictable disk IO delay is introduced, and emergency shutdown signal response timeout can be caused; When the abnormal processing of the page fault is carried out, the reading delay of the disk data of the hard page fault is influenced by the performance of an industrial storage medium (such as an industrial grade SSD (solid state drive), a CF (compact flash) card and the length of an on-site IO (input/output) queue, the page table mapping operation of the soft page fault is required to compete mmap_lock, the delay fluctuates along with the concurrency of an industrial task (such as multi-station synchronous control), and the strict time sequence of a control instruction is destroyed; In addition, in the 7×24-hour continuous operation scene of the industrial equipment, the dynamic accumulation of memory fragments can continuously amplify the uncertainty of allocation and recovery, while the kernel defragmentation operation can relieve fragments, the process of moving physical page data can occupy CPU and memory bandwidth, the execution time and time consumption can not be prejudged in advance, and the real-time control flow (such as production line beat synchronization) of the industrial site can be interfered. Aiming at hard real-time scenes such as industrial control, the existing Linux memory management technology has the remarkable defects that not only are links such as memory allocation, address conversion, cache interaction, recovery, page missing abnormality and the like have unpredictable delays, but also related optimization schemes are required to modify service application codes, the cost of adapting to stock maturation software is high, the period is long, and meanwhile, system-level optimization means lack of full-link cooperation at intervals, so that the requirement of delay certainty of the real-time scene on the memory is difficult to meet. However, there is no better overall solution for the above technical drawbacks. Disclosure of Invention Aiming at the problems, the invention provides a Preempt _RT-based memory instantaneity enhancement method to solve the problems of uncertain memory acces