CN-121618985-B - Anti-interference communication equipment and method capable of reconstructing frequency hopping pattern

CN121618985BCN 121618985 BCN121618985 BCN 121618985BCN-121618985-B

Abstract

The invention discloses a communication device and a method for anti-interference reconfigurable frequency hopping patterns, which relate to the technical field of wireless communication devices and comprise a baseband module and an intermediate frequency processing module which are based on a Field Programmable Gate Array (FPGA), and an AD conversion module, a DA conversion module, an up-conversion mixer and a down-conversion mixer which are connected with the Field Programmable Gate Array (FPGA), wherein the device forms a transmitting link and a receiving link.

Inventors

ZHANG CHUANGZHEN
LIU ZIHAO
ZHONG SHAN
ZHU YUYI

Assignees

深圳市科楠科技开发有限公司

Dates

Publication Date: 20260508
Application Date: 20260203

Claims (9)

1. The communication equipment with the anti-interference reconfigurable frequency hopping pattern is characterized by comprising a baseband module, an intermediate frequency processing module, an AD conversion module and a DA conversion module which are connected with the intermediate frequency processing module, and an up-conversion mixer and a down-conversion mixer which are connected with the baseband module, wherein the baseband module and the intermediate frequency processing module are based on a Field Programmable Gate Array (FPGA), the AD conversion module is connected with the down-conversion mixer, the up-conversion mixer is connected with the DA conversion module, and the equipment forms a transmitting link and a receiving link, wherein the transmitting link comprises an intermediate frequency data unpacking module, a channel coding module, a modulation module and a DA data transmitting module in the intermediate frequency processing module, and the DA conversion module and the up-conversion mixer, and the receiving link comprises the down-conversion mixer and the AD data acquisition module, a demodulation module, a channel decoding module and an intermediate frequency data packet module in the intermediate frequency processing module; The device further comprises a step of transmitting signals output by the up-conversion mixer in the transmitting link to the input end of the down-conversion mixer of the receiving link through an inner loop so as to allow the FPGA to perform self-loop test and performance verification on the transmitting link and the receiving link, wherein the step of performing self-loop test and performance verification on the transmitting link and the receiving link comprises the steps of transmitting self-checking data through the inner loop after loading a new frequency hopping pattern, verifying the correctness of the frequency hopping pattern, the modem function and the link integrity, and reporting the verification result to an upper computer; The demodulation module in the field programmable gate array FPGA is configured to estimate the frequency offset value of the carrier frequency and generate a frequency offset estimation signal when receiving the signal, and the field programmable gate array FPGA further comprises a frequency offset control module which is configured to perform closed loop fine tuning on the frequency of a clock crystal oscillator for providing a working clock for the field programmable gate array FPGA, the AD conversion module and the DA conversion module according to the frequency offset estimation signal until the frequency offset estimation signal converges to zero so as to realize frequency locking.
2. The communication device of claim 1, further comprising an adaptive power control mechanism comprising a power detection circuit and a programmable attenuator coupled to the transmit and receive links; the FPGA is configured to acquire the actual transmitting or receiving power value measured by the power detection circuit, compare the actual transmitting or receiving power value with a preset target power value, automatically adjust the attenuation value of the programmable attenuator according to the comparison result, and stabilize the signal power within the allowable error range of the target power value in a closed-loop mode.
3. The communication device of claim 2, wherein the field programmable gate array FPGA in the adaptive power control mechanism is configured to decrease the attenuation value of the programmable attenuator when the actual power value is less than the target power value and to increase the attenuation value of the programmable attenuator when the actual power value is greater than the target power value.
4. The communication device of claim 2, wherein the baseband module further comprises a baseband serial port receiving module, a baseband data parsing module, a baseband processing module, a baseband serial port transmitting module, a baseband data packet module, a frequency hopping control module, and a power adjustment module; The baseband data analysis module, the baseband data packet module, the frequency hopping control module and the power adjustment module are all connected with the baseband processing module, the baseband serial port receiving module is connected with the baseband data analysis module, and the baseband serial port transmitting module is connected with the baseband data packet module; The programmable attenuator comprises a down-conversion attenuator circuit and an up-conversion attenuator circuit, and the power adjustment module is connected with the power detection circuit, the down-conversion attenuator circuit and the up-conversion attenuator circuit; the frequency hopping control module is connected to the up-conversion mixer and the down-conversion mixer.
5. The communication device of claim 1, wherein the intermediate frequency processing module further comprises a channel decoding module; The channel decoding module is configured to perform RS decoding on the demodulated data to correct symbol errors in the data; The channel decoding module is further configured to perform CRC check on the data after RS decoding; The channel decoding module further comprises a decision logic configured to determine that the data is correct and reported if the CRC check passes, and to determine that the RS decoding is unsuccessful if the CRC check does not pass, and to mark the data as an error and report an error state.
6. The communication device of claim 5, wherein the intermediate frequency processing module further comprises an intermediate frequency data packet module, a demodulation module, an AD data acquisition module, an intermediate frequency data unpacking module, a channel coding module, a modulation module, a DA data transmission module, and an AD/DA configuration module; The AD data acquisition module is connected with the AD conversion module, and the intermediate frequency data packet module is connected to the baseband module; The intermediate frequency data unpacking module, the channel coding module, the modulation module and the DA data transmitting module are connected in sequence, the intermediate frequency data unpacking module is connected with the baseband module, and the DA data transmitting module is connected with the DA conversion module; The frequency offset control module is connected with the demodulation module, and the AD/DA configuration module is respectively connected with the AD conversion module and the DA conversion module.
7. A method for a communication device for interference-free reconfigurable frequency hopping pattern, the device comprising a field programmable gate array FPGA, an AD conversion module, a DA conversion module, an up-conversion mixer, and a down-conversion mixer, the method comprising the steps of: Self-loop verification, namely generating self-check data in the equipment in response to a self-check instruction, sequentially modulating, digital-to-analog converting and up-converting the data, then sending the up-converted signal to a down-conversion mixer and an AD conversion module through an inner loop, and carrying out demodulation and data comparison to verify the correctness of an internal transceiving link; the self-adaptive power control step comprises the steps of detecting the actual power on a signal path in real time in the signal transmitting or receiving process, comparing the actual power with a preset target power value, and automatically adjusting the attenuation value of a programmable attenuator on the signal path in a closed-loop mode according to the comparison result so as to ensure that the actual power is stabilized within the allowable error range of the target power value; And the automatic frequency offset control step is to periodically estimate the carrier frequency offset of the received signal when the signal is received and demodulated, and to perform closed loop fine tuning to the frequency of the clock crystal oscillator of the working clock provided by the FPGA, the AD conversion module and the DA conversion module according to the estimated frequency offset value until the estimated frequency offset value converges to zero so as to realize frequency locking.
8. The method for a communication device for interference-free reconfigurable frequency hopping pattern as claimed in claim 7, further comprising the step of error detection and repair, the step comprising: Performing RS decoding on the demodulated data to correct symbol errors present in the data; performing CRC on the RS-decoded data; If the CRC check fails, the RS decoding is judged to be unsuccessful, the data is marked as an error, and an error state is reported.
9. The method of claim 7, wherein the adaptive power control step comprises decreasing the attenuation value if the actual power is less than the target power, and increasing the attenuation value if the actual power is greater than the target power.

Description

Anti-interference communication equipment and method capable of reconstructing frequency hopping pattern Technical Field The present invention relates to the field of wireless communication devices, and more particularly, to a communication device and method for anti-interference reconfigurable frequency hopping pattern. Background In the technical field of modern wireless communication, in order to combat interference, improve anti-interception capability and realize multi-user access, frequency hopping technology is widely used. Traditional frequency hopping communication equipment is realized by adopting fixed hardware, and has the advantages of solidified functions and poor flexibility. With the development of software radio technology, schemes based on FPGA and digital processing are becoming mainstream, and flexibility and reconfigurability thereof are greatly enhanced. For example, chinese patent CN113472389B (hereinafter referred to as document 1) discloses a "low-latency, configurable wireless fast frequency hopping system based on FPGA". The system also utilizes the FPGA to realize baseband signal processing, including RS coding, DQPSK modulation, digital frequency hopping and the like, and realizes configurable frequency hopping communication by configuring parameters such as a frequency hopping table, a secret key and the like through an upper computer. The receiving end processes the signal through the DDC, the matched filtering and the frequency hopping synchronous module and performs gain control on the received signal through the AGC amplifier. However, document 1 and the prior art still have some drawbacks: 1. The system self-verification capability is not convenient, namely, after a new frequency hopping pattern or system parameters are loaded, the correctness of the file 1 can be verified through the cooperation of actual wireless receiving and transmitting equipment and opposite terminal equipment. This process is cumbersome and inconvenient for quick debugging in the development stage and reliability verification before deployment. 2. The power control mechanism is not fine enough, and the AGC amplifier mentioned in document 1 is an automatic gain control, the main purpose of which is to keep the amplitude of the receiver input signal within the optimum range of the AD conversion module, preventing signal clipping or excessive quantization noise. It is not an accurate closed loop power control system based on the target power value, and especially at the transmitting end, there is no description of accurate closed loop control of the transmit power. 3. The frequency offset correction mechanism is not perfect enough, and the frequency deviation among communication devices can seriously affect the demodulation performance. Carrier synchronization is mentioned in document 1, which is a conventional step of demodulation, but there is no explicit closed-loop control mechanism disclosed that can actively compensate and lock the system-level clock source frequency deviation. Therefore, there is an urgent need in the art for a comprehensive communication device that not only can implement high-performance frequency hopping communication, but also integrates the convenient self-verification capability, accurate self-adaptive power control, efficient error processing and robust automatic frequency offset correction functions, so as to comprehensively improve the reliability, maintainability and development efficiency of the system. Disclosure of Invention In order to overcome the defects of the prior art, the invention provides high-performance anti-interference reconfigurable frequency hopping communication equipment and a method integrating the functions of internal self-loop verification, self-adaptive power control and automatic frequency offset control. The invention solves the technical problems by adopting the technical scheme that the communication equipment with the anti-interference reconfigurable frequency hopping pattern is improved by comprising a baseband module and an intermediate frequency processing module which are based on a Field Programmable Gate Array (FPGA), an AD conversion module and a DA conversion module which are connected with the intermediate frequency processing module, and an up-conversion mixer and a down-conversion mixer which are connected with the baseband module, wherein the AD conversion module is connected with the down-conversion mixer, the up-conversion mixer is connected with the DA conversion module, and the equipment forms a transmitting link and a receiving link, and the equipment also comprises: Transmitting the signal output by the up-conversion mixer in the transmitting link to the input end of the down-conversion mixer of the receiving link through an inner loop so as to allow the field programmable gate array FPGA to perform self-loop test and performance verification on the transmitting link and the receiving link; The demodulation module in the