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CN-121641112-B - 10T-SRAM unit, read-write damage resistant dual-port SRAM circuit and chip

CN121641112BCN 121641112 BCN121641112 BCN 121641112BCN-121641112-B

Abstract

The invention relates to the field of integrated circuits, in particular to a 10T-SRAM unit, a dual-port SRAM circuit and a chip for resisting read-write damage. The 10T-SRAM unit is composed of 5 PMOS tubes P1-P5 and 5 NMOS tubes N1-N5. P1, P2, N1~ N4 constitute the 6T-SRAM that contains NMOS tube type data transmission channel, and the other constitution is by PMOS tube as another data transmission channel of transmission tube. The SRAM array of the dual-port SRAM circuit resistant to read-write damage is formed by arranging 10T-SRAM units upside down on a column-by-column basis, and the mode management circuit is used for adjusting the switching states of different data transmission channels of the 10T-SRAM units, so that signal interference among different units read-write in the same row does not exist. The invention solves the problem of read-write interference of the traditional SRAM circuit in read-write of the same row.

Inventors

  • DAI CHENGHU
  • MENG LEI
  • HAO LICAI
  • HU WEI
  • PENG CHUNYU
  • LU WENJUAN
  • LIN ZHITING
  • WU XIULONG

Assignees

  • 安徽大学

Dates

Publication Date
20260508
Application Date
20260130

Claims (10)

  1. 1. A10T-SRAM unit is characterized by comprising 5 PMOS tubes P1-P5 and 5 NMOS tubes N1-N5, wherein P1, P2, N1 and N2 are in inverse cross coupling to form a latch structure comprising a group of inverse storage nodes Q and QB, the source of P3 and N3 is connected with Q, the drain of P3 is connected with bit lines BL1 and BL2, the source of P4 and N4 is connected with QB, the drain of P4 is connected with bit lines BLB1 and BLB2, the gates of P3 and P4 are connected with the drain of P5 and the source of N5, the gates of P5 and N5 are connected with a gate control signal HPG, the source of P5 is connected with VDD and the drain of N5 is connected with one word line, and the gates of N3 and N4 are connected with the other word line; p3, P4 are used for forming a first read-write channel based on PMOS tube between latching structure and bit line BL1, BLB1, the on-off of the first read-write channel is managed jointly through the level state of the word line that HPG and N5 drain electrode connect, in order to make the circuit in read-write mode or keep the mode; n3, N4 are used for forming a second read-write channel based on NMOS tube between the latch structure and bit lines BL2, BLB2, the on-off of the second read-write channel is managed by the level state of the word line connected with the N3 grid.
  2. 2. The 10T-SRAM cell of claim 1, wherein: In the first read-write channel, when the gate control signal HPG is in a high level and the word line connected with the N5 drain electrode is in a low level, the circuit is in a read-write mode, and P3 and P4 are conducted; In the second read-write channel, when the word line connected with the N3 grid is at a high level, the circuit is in a read-write mode, N3 and N4 are conducted, and when the word line connected with the N3 grid is at a low level, the circuit is in a hold mode, and N3 and N4 are turned off.
  3. 3. A dual port SRAM circuit resistant to read and write corruption comprising: an SRAM array formed by arranging a plurality of 10T-SRAM cell arrays as claimed in claim 1 or 2, wherein the 10T-SRAM cells in the same column share bit lines BL1, BL2, BLB1 and BLB2, the 10T-SRAM cells in the same column share word lines WLA and WLB, P3 and P4 in the 10T-SRAM cells in the odd columns are positioned above, N3 and N4 are positioned below, and the drains of N5 are connected with word lines WLA, P5 and N5 are connected with HPGA, P3 and P4 in the 10T-SRAM cells in even columns are positioned below, N3 and N4 are positioned above, and the drains of N5 are connected with the gates of word lines WLB, P5 and N5 are connected with HPGB; A column decoder A, each bit of the output signal of which is used for controlling the connection state of the bit lines BL1 and BLB1 of each odd column 10T-SRAM unit and the comparator, and controlling the connection state of the bit lines BL2 and BLB2 of each even column 10T-SRAM unit and the comparator; A column decoder B for controlling the connection state of the bit lines BL2 and BLB2 of the odd-numbered columns 10T-SRAM cells and the comparator, and for controlling the connection state of the bit lines BL1 and BLB1 of the even-numbered columns 10T-SRAM cells and the comparator, respectively, in each bit of the output signal thereof; A row decoder a for outputting a word line driving signal ENA applied to the word line WLA; a row decoder B for outputting a word line driving signal ENB acting on the word line WLB; the mode management circuit comprises a management unit corresponding to each row in the SRAM array, wherein the management unit comprises 4 AND gates AND 1-AND 4 AND1 inverters INV1, two input ends of the AND1 are respectively connected with ENA AND a clock signal CLK, the output signal of the AND1 is HPGA AND is connected with the grid electrode of N5 of the 10T-SRAM unit of all odd columns in the current row, one input end of the AND2 is connected with the ENA, the input end of the INV1 is connected with the lowest bit of the input signal of the decoder A, the output end of the AND2 is connected with a word line WLA, two input ends of the AND3 are respectively connected with ENB AND the clock signal CLK, the output signal of the AND3 is HPGB AND is connected with the grid electrode of N5 of the 10T-SRAM unit of all even columns in the current row, one input end of the AND4 is connected with the word line WLB, one group of the output ends of the AND4 is directly connected between the other input ends of the decoders A AND the AND2, AND the other input ends of the decoders B AND the AND4 are connected with the other input ends of the AND4 through the INV 1.
  4. 4. The dual port SRAM circuit of claim 3, wherein when performing parallel read and write operations on two different 10T-SRAM cells in a same row and belonging to an odd column and an even column of the memory array, The management units of the corresponding rows in the mode management circuit are used for adjusting the level states of HPGA, HPGB, WLA and WLB, keeping the level states of HPGA and HPGB synchronous, keeping the level states of WLA and WLB synchronous, and further enabling two 10T-SRAM units to execute respective data read-write tasks only through a first read-write channel or through a second read-write channel at the same time.
  5. 5. The dual port SRAM circuit of claim 4, wherein said dual port SRAM circuit is resistant to read and write corruption: When HPGA= HPGB =1, if WLA=WLB=0, the first read-write channel of the 10T-SRAM unit in the odd columns is in a read-write mode, and the second read-write channel is in a hold mode; When HPGA= HPGB =1, if WLA=WLB=1, the first read-write channel of the 10T-SRAM unit in the odd columns is in a holding mode, and the second read-write channel is in a read-write mode; When hpga= HPGB =0, wla=wlb=0, and at this time, the first read/write channel of the 10T-SRAM cell in the odd column is in the hold mode, the second read/write channel is in the hold mode, and the first read/write channel of the 10T-SRAM cell in the even column is in the hold mode, and the second read/write channel is in the hold mode.
  6. 6. The dual-port SRAM circuit of claim 3, wherein the second read/write channels of the 10T-SRAM cells of all even columns are in a read/write mode when the word line WLA in any one row is at a high level; The second read/write channels of all odd columns of 10T-SRAM cells are in a read/write mode when the word line WLB in any one row is at a high level, and the second read/write channels of all odd columns of 10T-SRAM cells are in a hold mode when the word line WLB in any one row is at a low level.
  7. 7. The dual port SRAM circuit of claim 3, wherein when only one of the rows is selected for performing a read/write operation, the level states of the least significant bits of column decoder A and column decoder B remain inverted; When a first read-write channel of an odd number column in any row is selected to execute data read-write operation, the output ENA of a row decoder A of a corresponding row is high level; when the second read-write channel of the odd columns in any row is selected to perform data read-write operation, the output ENB of the row decoder B of the corresponding row is at a high level, and the lowest bit of the input signal of the column decoder B is at a high level.
  8. 8. The dual-port SRAM circuit of claim 7, wherein when a data read/write operation is performed by selecting a first read/write channel of an even column in any one row, an output ENB of a row decoder B of the corresponding row is high level; when the second read-write channel of even columns in any row is selected to perform data read-write operation, the output ENA of the row decoder A of the corresponding row is high level, and the lowest bit of the input signal of the column decoder A is high level.
  9. 9. The dual-port SRAM circuit of claim 7, wherein when the output ENA of the row decoder A and the output ENB of the row decoder B of any row are both high, the circuit is in the synchronous read-write mode; when one of the output ENA of the row decoder a and the output ENB of the row decoder B of any one row is at a low level while the other is at a high level, the circuit is in a non-synchronous read-write mode.
  10. 10. A memory chip, characterized in that it is packaged by a dual-port SRAM circuit as claimed in any one of claims 3-9, which is resistant to read-write damages.

Description

10T-SRAM unit, read-write damage resistant dual-port SRAM circuit and chip Technical Field The invention relates to the field of integrated circuits, in particular to a 10T-SRAM unit, a dual-port SRAM circuit resistant to read-write damage and a corresponding chip thereof. Background The traditional 8T SRAM is characterized in that a set of NMOS (N-channel metal oxide semiconductor) tubes used as a transmission tube read-write path are added on the basis of the 6T SRAM, and the problems of read-write of the same row are not thoroughly solved all the time. When two sets of decoding of the dual port select the same row, the problem of read-write damage can be caused. FIG. 1 illustrates the read disturb problem in a typical peer access, in which when all access pipes of a memory cell performing a read operation are open, the RSNM of the cell will drop more greatly, known as read disturb. FIG. 2 illustrates the problem of write disturb in a typical peer-to-peer access, which is also referred to as write disturb, as a dummy read operation may cause difficulty in writing data to the memory cells performing the write operation. Obviously, if in the SRAM circuit of one sampling dual-port SRAM cell, only one of the two read-write paths of the two dual-port SRAM cells of the same row and different columns is conducted when the read-write tasks are simultaneously executed, and the read-write paths conducted respectively are associated with different word lines and bit lines, the above-mentioned problems of read interference and write interference can be avoided in the read-write of the same row. However, the prior art does not have a circuit scheme capable of achieving this technical effect. Disclosure of Invention In order to solve the problem of read-write interference of SRAM circuits in the same row of read-write, the invention provides a 10T-SRAM unit, a dual-port SRAM circuit resistant to read-write damage and a corresponding chip thereof. The technical scheme provided by the invention is as follows: A10T-SRAM cell includes 5 PMOS tubes P1-P5 and 5 NMOS tubes N1-N5. Wherein P1, P2, N1, N2 are inversely cross-coupled to form a latch structure comprising a set of inverted storage nodes Q and QB. The source of P3 and N3 is connected to Q, and the drain of P3 is connected to bit line BL1, and the drain of N3 is connected to bit line BL 2. The source of P4 and N4 is connected to QB, and the drain of P4 is connected to bit line BLB1 and the drain of N4 is connected to bit line BLB 2. The gates of P3 and P4 are connected with the drain electrode of P5 and the source electrode of N5, the gates of P5 and N5 are connected with a gate control signal HPG, the source electrode of P5 is connected with VDD, the drain electrode of N5 is connected with one word line, and the gates of N3 and N4 are connected with the other word line. And P3 and P4 are used for forming a first read-write channel based on a PMOS tube between the latch structure and the bit lines BL1 and BLB1, and the on-off of the first read-write channel is managed together by the level state voltage of the word line connected with the drains of the HPG and N5. N3, N4 are used for forming a second read-write channel based on NMOS tube between the latch structure and bit lines BL2, BLB2, the on-off of the second read-write channel is managed by the level state of the word line connected with the N3 grid. As a further improvement of the invention, in the first read-write channel, when the gate control signal HPG is at a high level and the word line connected with the drain electrode N5 is at a low level, the circuit is in a read-write mode, and P3 and P4 are conducted. When the gate control signal HPG is low level and/or the word line connected with the drain electrode of N5 is high level, the circuit is in a hold mode, and P3 and P4 are turned off. In the second read-write channel, when the word line connected with the N3 grid is at a high level, the circuit is in a read-write mode, and N3 and N4 are conducted. When the word line connected with the N3 grid electrode is in a low level, the circuit is in a holding mode, and N3 and N4 are turned off. The invention also comprises a dual-port SRAM circuit resistant to read-write damage, which comprises an SRAM array, a column decoder A, a column decoder B, a row decoder A, a row decoder B and a mode management circuit. The SRAM array is formed by arranging a plurality of 10T-SRAM cell arrays. The 10T-SRAM cells of the same column share bit lines BL1, BL2, BLB1, BLB2, and the 10T-SRAM cells of the same column share word lines WLA and WLB. Wherein P3, P4 in each 10T-SRAM cell in the odd columns are located above, N3, N4 are located below, and the drains of N5 are connected to word line WLA, and the gates of P5, N5 are connected to HPGA. P3, P4 in each 10T-SRAM cell in even columns are located below, N3, N4 are located above, and the drains of N5 are connected to word line WLB, and the gates of P5, N5 are connected HPGB. T