CN-121641139-B - Resistor calibration circuit, memory and electronic equipment

CN121641139BCN 121641139 BCN121641139 BCN 121641139BCN-121641139-B

Abstract

The invention relates to the technical field of semiconductors, and provides a resistor calibration circuit, a memory and electronic equipment, aiming at the problem of locking errors of a resistance calibration code caused by improper sending time of a ZQ (zero-zero) latch command, wherein the resistor calibration circuit comprises a main calibration circuit and a control circuit, wherein the main calibration circuit is configured to adjust the resistance calibration code in the ZQ calibration process; the system comprises a state machine configured to generate a calibration state signal, a latch control circuit configured to receive a ZQ latch command, perform logic processing on the ZQ latch command and the calibration state signal to generate a target latch command, synchronize or delay the pulse trailing edge of the target latch command with the target edge of the calibration state signal, and a latch circuit configured to latch the resistance calibration code in response to the pulse trailing edge of the target latch command to generate a target calibration code, so that the target latch command is utilized to latch the resistance calibration code instead of directly utilizing the ZQ latch command, the locking accuracy of the resistance calibration code is improved, and the stability of the memory is improved.

Inventors

LI HONGWEN
RAO HAN

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260203

Claims (12)

1. A resistance calibration circuit, the resistance calibration circuit comprising: The main calibration circuit is configured to adjust the resistance calibration code in the ZQ calibration process until the resistance of the target resistor meets a preset condition, wherein the resistance calibration code is used for adjusting the resistance of the target resistor; The system comprises a state machine, a first state and a second state, wherein the state machine is configured to generate a calibration state signal of a first state in the ZQ calibration process; The latch control circuit is connected with the state machine and is configured to receive a ZQ latch command and the calibration state signal, and perform logic processing on the ZQ latch command and the calibration state signal to generate a target latch command, wherein the pulse trailing edge of the target latch command is synchronous or delayed to the target edge of the calibration state signal, and the target edge is changed from the first state to the second state; And the latch circuit is connected with the latch control circuit and the main calibration circuit and is configured to receive the target latch command and the resistance calibration code, latch the resistance calibration code in response to the pulse trailing edge of the target latch command and generate a target calibration code.
2. The resistor calibration circuit of claim 1, wherein, The main calibration circuit is further configured to output an update code pulse when the ZQ calibration process meets a preset calibration end condition, wherein the pulse leading edge of the update code pulse is ahead of the target edge of the calibration state signal; the latch circuit includes; the first latch circuit is connected with the main calibration circuit and is configured to receive the update code pulse and the resistance calibration code, latch the resistance calibration code in response to the pulse front edge of the update code pulse and generate an update calibration code; and the second latch circuit is connected with the first latch circuit and is configured to receive the target latch command and the updated calibration code, latch the updated calibration code in response to the pulse trailing edge of the target latch command and generate a target calibration code.
3. A resistor calibration circuit according to claim 2, wherein, The latch control circuit is specifically configured to, if the ZQ latch command is received during a period when the calibration state signal is in a first state, pulse-broaden the ZQ latch command by using the calibration state signal to generate the target latch command; Or if the ZQ latch command is received during the period when the calibration state signal is in the second state, outputting the ZQ latch command as the target latch command.
4. The resistor calibration circuit of claim 2, wherein the latch control circuit comprises: a logic circuit configured to pulse-broaden the ZQ latch command with the calibration status signal, outputting an intermediate broaden signal; And the selection circuit is connected with the logic circuit and is configured to output the received intermediate widening signal as the target latch command in the period when the calibration state signal is in the first state, and output the received ZQ latch command as the target latch command in the period when the calibration state signal is in the second state.
5. The resistor calibration circuit of claim 4, wherein, The logic circuit is specifically configured to adjust the intermediate widening signal to a third state in response to the ZQ latch command during the calibration state signal being the first state; And adjusting the intermediate widening signal to a fourth state when the calibration state signal changes from the first state to the second state.
6. The resistor calibration circuit of claim 4, wherein, in the case where the first state and the third state are both high: The logic circuit comprises a first NAND gate and a first trigger, wherein two input ends of the first NAND gate respectively receive the calibration state signal and the ZQ latching command, the input end of the first trigger receives a preset level signal, the clock end of the first trigger receives the calibration clock signal, the setting end of the first trigger is connected with the output end of the first NAND gate, the reset end of the first trigger receives the calibration state signal, and the setting end and the reset end are both in low level effect.
7. The resistor calibration circuit according to any one of claims 2 to 6, wherein the resistance calibration code includes a pull-up calibration code and a pull-down calibration code; The main calibration circuit is specifically configured to respond to a pull-down enabling signal in an enabling state and adjust the pull-down calibration code until the pull-down resistor meets a preset condition; the state machine is specifically configured to adjust the calibration state signal to a first state in response to a change of the pull-down enable signal from an enabled state to an enabled state; The ZQ calibration process comprises a pull-down calibration stage and a pull-up calibration stage, wherein in the pull-down calibration stage, the pull-down enabling signal is in an enabling state, the pull-up enabling signal is in a non-enabling state, and in the pull-up calibration stage, the pull-down enabling signal is in the non-enabling state, and the pull-up enabling signal is in an enabling state.
8. The resistive calibration circuit of claim 7, wherein the main calibration circuit comprises: The resistor and comparison module comprises the pull-down resistor, is configured to receive and utilize the pull-down calibration code to regulate and control the resistance value of the pull-down resistor, compares the resistance value of the pull-down resistor with a standard resistance value during the period that the pull-down enabling signal is in an enabling state, and outputs a comparison signal; the adjusting module is connected with the resistor and the comparing module and is configured to receive the comparing signal, and in each calibration period, the pull-down calibration code is adjusted once based on the comparing signal during the period that the pull-down enabling signal is in an enabling state; The resistor and comparison module further comprises the pull-up resistor and is further configured to receive and utilize the pull-up calibration code to regulate and control the resistance value of the pull-up resistor; The adjustment module is configured to receive the comparison signal, and in each calibration period, the pull-up calibration code is adjusted once based on the comparison signal during the period that the pull-up enabling signal is in an enabling state.
9. The resistive calibration circuit of claim 8, wherein the main calibration circuit comprises: the control module is connected with the adjustment module and is configured to output a calibration clock signal, and is used for counting the period of the calibration clock signal and outputting an update code pulse based on the rising edge of the calibration clock signal under the condition that the count value is a preset threshold value; the first latch circuit comprises a second trigger and a third trigger, and the second latch circuit comprises a fourth trigger and a fifth trigger; The input end of the second trigger receives the pull-up calibration code, and the clock end of the second trigger receives the update code pulse; the input end of the third trigger receives the pull-down calibration code, and the clock end of the third trigger receives the update code pulse; the input end of the fourth trigger is connected with the output end of the second trigger, the clock end of the fourth trigger receives the target latch command, and the fourth trigger outputs a target pull-up calibration code; the input end of the fifth trigger is connected with the output end of the third trigger, the clock end of the fifth trigger receives the target latch command, and the clock end of the fifth trigger outputs a target pull-down calibration code; the target pull-up calibration code and the target pull-down calibration code jointly form the target calibration code.
10. The resistor calibration circuit of claim 8, wherein the resistor and compare module comprises: The resistor module comprises the pull-up resistor, the pull-down resistor and a standard resistor and is configured to output a first voltage and a second voltage, wherein the first voltage indicates the voltage division result of the pull-down resistor and the standard resistor, and the second voltage indicates the voltage division result of the pull-up resistor and the pull-down resistor; And a comparison circuit configured to compare a pull-down reference voltage with the first voltage in response to the pull-down enable signal of an enable state, and to compare the pull-up reference voltage with the second voltage in response to the pull-up enable signal of an enable state, and to generate the comparison signal.
11. A memory comprising a resistance calibration circuit as claimed in any one of claims 1 to 10.
12. An electronic device comprising the memory of claim 11.

Description

Resistor calibration circuit, memory and electronic equipment Technical Field The present disclosure relates to semiconductor technology, and more particularly, to a resistance calibration circuit, a memory, and an electronic device. Background There are some adjustable resistors in the memory for output driving and signal termination, the resistance values of these resistors need to be calibrated to match different working environments, the above calibration process is called ZQ calibration, and the signal for adjusting the adjustable resistor is called resistance calibration code. After the memory performs ZQ calibration, it is necessary to wait for a ZQ latch command sent by a System on Chip (SoC) and latch the resistance calibration code based on the ZQ latch command. However, because the ZQ calibration mechanism is not perfect, the sending timing of the ZQ latch command is not proper in part of the scenes, so that the ZQ latch command is latched to the wrong resistance calibration code, and the performance of the memory is affected. Disclosure of Invention The embodiment of the disclosure provides a resistance calibration circuit, a memory and an electronic device. The technical scheme of the embodiment of the disclosure is realized as follows: In a first aspect, embodiments of the present disclosure provide a resistance calibration circuit comprising: The main calibration circuit is configured to adjust the resistance calibration code in the ZQ calibration process until the resistance of the target resistor meets a preset condition, wherein the resistance calibration code is used for adjusting the resistance of the target resistor; The system comprises a state machine, a first state and a second state, wherein the state machine is configured to generate a calibration state signal of a first state in the ZQ calibration process; The latch control circuit is connected with the state machine and is configured to receive a ZQ latch command and the calibration state signal, and perform logic processing on the ZQ latch command and the calibration state signal to generate a target latch command, wherein the pulse trailing edge of the target latch command is synchronous or delayed to the target edge of the calibration state signal, and the target edge is changed from the first state to the second state; And the latch circuit is connected with the latch control circuit and the main calibration circuit and is configured to receive the target latch command and the resistance calibration code, latch the resistance calibration code in response to the pulse trailing edge of the target latch command and generate a target calibration code. In some embodiments, the master calibration circuit is further configured to output an update code pulse if the ZQ calibration process meets a preset calibration end condition, wherein a pulse leading edge of the update code pulse is ahead of a target edge of the calibration status signal; the first latch circuit is connected with the main calibration circuit and is configured to receive the update code pulse and the resistance calibration code, latch the resistance calibration code in response to the pulse front edge of the update code pulse and generate an update calibration code; and the second latch circuit is connected with the first latch circuit and is configured to receive the target latch command and the updated calibration code, latch the updated calibration code in response to the pulse trailing edge of the target latch command and generate a target calibration code. In some embodiments, the latch control circuit is specifically configured to pulse-broaden the ZQ latch command with the calibration status signal if the ZQ latch command is received during a period when the calibration status signal is in a first state, to generate the target latch command, or to output the ZQ latch command as the target latch command if the ZQ latch command is received during a period when the calibration status signal is in a second state. In some embodiments, the latch control circuit comprises a logic circuit configured to pulse-broaden the ZQ latch command with the calibration state signal and output an intermediate broaden signal, a selection circuit coupled to the logic circuit and configured to output the received intermediate broaden signal as the target latch command during a period when the calibration state signal is in a first state, and output the received ZQ latch command as the target latch command during a period when the calibration state signal is in a second state. In some embodiments, the logic is specifically configured to adjust the intermediate widening signal to a third state in response to the ZQ latch command during a first state of the calibration state signal, and to adjust the intermediate widening signal to a fourth state if the calibration state signal changes from the first state to a second state. In some embodiments, when the first state and the third state