CN-121643699-B - FIR filter design method based on loop resistance real-time calculation

CN121643699BCN 121643699 BCN121643699 BCN 121643699BCN-121643699-B

Abstract

The invention relates to the technical field of power equipment state monitoring and discloses a method for designing an FIR filter based on loop resistance real-time calculation, which comprises the steps of firstly establishing a mapping rule from a prototype coefficient to a multiphase sub-filter bank, and constructing linear control conditions for defining strict alignment of the energy gravity center of each branch and nominal group delay; then, an optimal approximation correction is performed on the initial coefficients generated from the frequency domain indices using a coefficient corrector containing the control conditions, thereby obtaining target filter coefficients. The invention can eliminate periodic interference introduced by channel switching from the source while maintaining high-frequency response details, thereby greatly improving the accuracy and reliability of loop resistance on-line monitoring data.

Inventors

Pan Yinlian
ZHANG YANG
REN WEIDONG
GU LIQIANG

Assignees

南京固攀自动化科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260204

Claims (4)

1. The design method of the FIR filter based on the real-time calculation of the loop resistance is characterized by comprising the following steps: Establishing a digital signal processing link comprising anti-aliasing filtering and downsampling processing, and establishing a coefficient allocation rule for a prototype filter coefficient to a multi-rate signal decimation structure, wherein the multi-rate signal decimation structure comprises a plurality of parallel processing branches corresponding to different sampling instants, comprising: Obtaining a prototype filter coefficient sequence, and setting a downsampling factor as a modulus of multiphase decomposition; performing modular operation on the downsampling factor by using an index value according to the index sequence of the prototype filter coefficient sequence; Dividing prototype filter coefficients with the same modular operation result into the same parallel processing branch as a sub-filter coefficient sequence of the parallel processing branch, thereby mapping a single group of prototype filter coefficients into a sub-filter coefficient sequence of a plurality of groups of parallel processing branches; setting a branch delay consistency control condition for limiting that an impulse response weighted delay center of each parallel processing branch is consistent with a nominal group delay of the prototype filter so as to eliminate false fluctuation of a resistance change rate caused by multiphase switch switching, wherein the method comprises the following steps: Respectively calculating a time index weighted first moment and a coefficient value sum of a sub-filter coefficient sequence of each parallel processing branch; Calculating the ratio of the overall time index weighted first moment of the prototype filter coefficient to the total numerical value of the overall coefficient, and taking the ratio as the nominal group delay; constructing a linear constraint equation, and defining the product of the time index weighted first moment of each parallel processing branch minus the nominal group delay and the coefficient numerical sum of the branch to be equal to zero, thereby ensuring that the time barycenters of all the parallel processing branches are kept aligned under the view angle of downsampling output; Generating an initial filter coefficient according to a preset frequency domain response index, and executing optimal approximation correction operation on the initial filter coefficient by using a coefficient correction operator containing the branch delay consistency control condition to obtain a target filter coefficient, wherein the method comprises the following steps: Constructing a linear phase symmetry constraint matrix for defining filter coefficients to satisfy a central symmetry characteristic to ensure an overall linear phase; Combining the linear phase symmetry constraint matrix with a matrix constructed based on the branch delay consistency control condition to form a comprehensive linear constraint matrix; Constructing a least square orthogonal projection operator based on the comprehensive linear constraint matrix, calculating a projection vector of the initial filter coefficient under all constraint conditions by using the least square orthogonal projection operator, and overlapping the projection vector to the initial filter coefficient or directly serving as a correction result, thereby obtaining a target filter coefficient meeting the frequency domain response index and meeting the consistency of branch delay; And configuring a downsampling module of the digital signal processor based on the target filter coefficient to synchronously process the voltage and current signals so as to output a real-time loop resistance value for eliminating the sampling phase related interference.
2. The method for designing a FIR filter based on real-time calculation of loop resistance according to claim 1, wherein establishing a digital signal processing link including anti-aliasing filtering and downsampling processing comprises: Respectively taking a voltage digital sequence and a current digital sequence which are acquired in real time as input signals, and carrying out convolution filtering processing on the input signals by using the same group of target filter coefficients; Performing equidistant extraction operation on the filtered voltage signal and the filtered current signal according to a preset downsampling factor to respectively generate a downsampled voltage sequence and a downsampled current sequence; Dividing the downsampled voltage sequence value at each sampling moment by the corresponding downsampled current sequence value, and calculating to obtain a real-time loop resistance sequence.
3. The method for designing an FIR filter based on real-time calculation of loop resistance according to claim 1, wherein generating initial filter coefficients according to a preset frequency domain response index comprises: determining passband cut-off frequency, stopband starting frequency and weighting error coefficients of each frequency band for anti-aliasing filtering; And calculating a group of finite length sequences meeting the requirements of the passband cut-off frequency and the stopband starting frequency and minimizing the maximum weighted error in the frequency domain by adopting a Chebyshev optimal consistent approximation algorithm, and taking the finite length sequences as initial filter coefficients.
4. The method of claim 1, wherein configuring the downsampling module of the digital signal processor to synchronize the voltage and current signals based on the target filter coefficients to output a real-time loop resistance value that eliminates sampling phase-related disturbances comprises: According to a coefficient distribution rule, recombining the target filter coefficient into a plurality of groups of sub-filter coefficient sequences of parallel processing branches; loading a plurality of groups of sub-filter coefficient sequences into corresponding registers of a multi-rate signal extraction structure of a digital signal processor respectively; And controlling the multi-rate signal extraction structure to perform multiphase filtering and downsampling on the voltage signal and the current signal which are input in real time, outputting a downsampled voltage sequence and a downsampled current sequence, and calculating the ratio of the downsampled voltage sequence to the downsampled current sequence to obtain a real-time loop resistance value for eliminating trend differential term periodic modulation caused by the deviation of the center of gravity of the branch time.

Description

FIR filter design method based on loop resistance real-time calculation Technical Field The invention relates to the technical field of power equipment state monitoring, in particular to a method for designing an FIR filter based on loop resistance real-time calculation. Background In an operation and maintenance system of the smart grid, loop resistance is a key index for evaluating the current-carrying loop connection state, contact wear degree and oxidation condition of the power equipment. With the evolution of monitoring technology, the traditional offline periodic maintenance mode is gradually changed to an online monitoring and dynamic resistance measurement mode. The application generally adopts the principle of a millivolt voltage drop method, namely, a loop current signal and voltage drop signals at two ends of a contact are synchronously collected, and the ratio of the loop current signal to the voltage drop signals at two ends of the contact is calculated through numerical operation so as to obtain a real-time resistance value. Because of the complex environment of the electric power field, the collected original signals are often mixed with stronger power frequency interference, high-frequency transient noise generated by switching action and various electromagnetic interferences. Therefore, prior to calculating the resistance ratio, a Finite Impulse Response (FIR) filter is typically required to be configured in the digital signal processing link for anti-aliasing processing, in combination with a downsampling technique to reduce the data throughput pressure of the subsequent processing unit. In engineering realization, in order to save hardware logic resources and reduce operation power consumption, a multiphase decomposition structure is widely adopted to realize synchronous operation of filtering and downsampling. The structure divides input data into a plurality of parallel sub-filter branches for processing through a commutator. However, existing FIR filter designs typically only focus on frequency domain response indicators, such as passband ripple, stopband attenuation magnitude, and overall linear phase properties. In the multiphase downsampling architecture, the conventional design concept has a defect that after coefficients of a prototype filter are mapped to a plurality of sub-filter branches, energy centers (i.e., weighted delay centers) of the branches in time domain are not consistent. Under the actual working condition of on-line monitoring of loop resistance, the inconsistency of the center of gravity among the branches can cause periodic deviation of the effective sampling time of the system to the input signal due to the periodic channel switching mechanism of the multiphase structure during operation. When the actual loop resistance exhibits a tendency to change smoothly due to device temperature rise or contact movement, such periodic deviations can erroneously convert the rate of change of resistance (i.e., the slope of the trend) to pseudo-periodic fluctuations that are synchronized with the downsampling factor. Such spurious fluctuations can severely interfere with the operation and maintenance system's judgment of the health of the device. For example, it may mask weak early signs of contact degradation or be misinterpreted as oscillations caused by poor device contact. The traditional countermeasure is to add a smooth filtering link at the back end, but this introduces extra measurement delay obviously, so that the system cannot capture the rapid change details in the action process of the circuit breaker in time, and the timeliness requirement of dynamic measurement is difficult to meet. Disclosure of Invention The invention provides a method for designing an FIR filter based on loop resistance real-time calculation, which solves the technical problems in the background technology. The invention provides a method for designing an FIR filter based on loop resistance real-time calculation, which comprises the following steps: Establishing a digital signal processing link comprising anti-aliasing filtering and downsampling processing, and establishing a coefficient allocation rule of a prototype filter coefficient to a multi-rate signal extraction structure, wherein the multi-rate signal extraction structure comprises a plurality of parallel processing branches corresponding to different sampling moments; Setting a branch delay consistency control condition for limiting that the impulse response weighted delay center of each parallel processing branch is consistent with the nominal group delay of the prototype filter so as to eliminate the false fluctuation of the resistance change rate caused by multiphase switch switching; generating an initial filter coefficient according to a preset frequency domain response index, and executing optimal approximation correction operation on the initial filter coefficient by using a coefficient correction operator containing the bran