CN-121643765-B - Incremental analog-to-digital converter based on passive noise shaping and signal processing method

CN121643765BCN 121643765 BCN121643765 BCN 121643765BCN-121643765-B

Abstract

The invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method, which can be applied to the technical field of quantization. The incremental analog-to-digital converter comprises an input integrating circuit, a passive amplifying circuit, a passive noise shaping circuit, a quantization circuit and a quantization circuit, wherein the input integrating circuit is configured to generate a j-1 th low-order integrating voltage according to an input signal from a signal input end, generate a k high-order integrating voltage according to the input signal, the passive amplifying circuit is configured to obtain a k gain voltage according to the k high-order integrating voltage based on a preset amplifying coefficient, the passive noise shaping circuit is configured to passively integrate the k high-order integrating voltage to obtain a k passive integrating voltage, the k passive integrating voltage is utilized to passively gain the k passive integrating voltage to obtain a k high-order gain voltage, the quantization circuit is configured to respectively quantize M1 low-order integrating voltages in M1 cycles to generate M1 coarse quantized values, and respectively quantize M2 high-order gain voltages in M2 cycles to generate M2 fine quantized values.

Inventors

WANG JING
LIU SHASHA
CHENG LIN

Assignees

中国科学技术大学

Dates

Publication Date: 20260508
Application Date: 20260203

Claims (12)

1. An incremental analog-to-digital converter based on passive noise shaping, comprising: An input integrating circuit configured to generate a j-th low-order integrated voltage according to an input signal from a signal input terminal under control of a j-1-th coarse quantization value in a j-th period of M1 periods, and generate a k-th high-order integrated voltage according to the input signal in a k-th period of M2 periods after the M1 periods under control of a k-1-th fine quantization value, wherein j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k; A passive amplification circuit configured to obtain a kth gain voltage from a kth high-order integrated voltage based on a predetermined amplification factor in an integration phase of a kth period; The passive noise shaping circuit is configured to perform passive integration on the kth high-order integrated voltage in the integration stage to obtain a kth passive integrated voltage, and is electrically connected with the passive amplifying circuit in the gain stage of the kth period so as to perform passive gain on the kth passive integrated voltage by using the kth gain voltage to obtain a kth high-order gain voltage; And a quantization circuit configured to quantize the M1 low-order integrated voltages respectively in M1 periods to generate M1 coarse quantized values, and to quantize the M2 high-order gain voltages respectively in M2 periods to generate M2 fine quantized values, wherein the fine quantized values have higher precision than the coarse quantized values.
2. The incremental analog-to-digital converter of claim 1 wherein the signal input is a differential input; The input integrating circuit, the passive amplifying circuit and the passive noise shaping circuit are electrically connected; The passive amplifying circuit comprises a plurality of capacitors, wherein the capacitors receive the kth high-order integrated voltage and charge the kth high-order integrated voltage in the integrating stage, and the capacitors are charged to jointly provide the kth gain voltage to the passive noise shaping circuit in the gain stage based on the preset amplifying coefficient.
3. The incremental analog-to-digital converter of claim 2 wherein the plurality of capacitors comprises I first capacitors and I second capacitors, I being an integer greater than 1; the k high-order integral voltage comprises a k residual positive voltage provided by the positive output end of the input integral circuit and a k residual negative voltage provided by the negative output end of the input integral circuit; The positive output end of the input integrating circuit and the first ends of the I first capacitors are configured to be electrically connected in the integrating stage, the negative output end of the input integrating circuit and the first ends of the I second capacitors are configured to be electrically connected so that the I first capacitors charge the I first capacitors through the k residual positive voltage, and the I second capacitors charge the I second capacitors through the k residual negative voltage; the predetermined amplification factor includes a first amplification factor and a second amplification factor, the first amplification factor corresponding to a capacitance value of the I first capacitances, the second amplification factor corresponding to a capacitance value of the I second capacitances, the first end of the passive noise shaping circuit and the first end of the I first capacitances configured to be electrically connected during the gain phase, the second end of the passive noise shaping circuit and the first end of the I second capacitances configured to be electrically connected such that the charged I first capacitances and the charged I second capacitances together provide the kth gain voltage to the passive noise shaping circuit.
4. The incremental analog-to-digital converter of claim 2 further comprising: A first gain switch electrically connected between a first output of the passive amplification circuit and a first end of the passive noise shaping circuit; A second gain switch electrically connected between a second output of the passive amplification circuit and a second end of the passive noise shaping circuit; Wherein the first and second gain switches are configured to open during the integration phase to electrically disconnect the passive amplification circuit from the passive noise shaping circuit and to close during the gain phase to receive the kth gain voltage from the passive amplification circuit.
5. The incremental analog-to-digital converter of claim 3 wherein the digital signal processing unit, During the gain phase, a portion of the I first capacitors charged are configured to be in parallel with each other and connected between a further portion of the first capacitors and the common mode terminal to be in series with the further portion of the first capacitors so that the I first capacitors provide the kth residual positive voltage to the passive noise shaping circuit; During the gain phase, a portion of the I second capacitors charged are configured to be in parallel with each other and connected between a further portion of the second capacitors and the common mode terminal to be in series with the further portion of the second capacitors so that the I second capacitors provide the kth residual negative voltage to the passive noise shaping circuit.
6. The incremental analog-to-digital converter of claim 5 further comprising: A first parallel switch electrically connected between first ends of adjacent ones of the partial first capacitances, a second parallel switch electrically connected between second ends of adjacent ones of the partial first capacitances, a first ground switch electrically connected between the second ends of the partial first capacitances and the common mode terminal, a first series switch electrically connected between the second ends of the partial first capacitances and the first ends of the other partial first capacitances, the second ends of the other partial first capacitances being directly electrically connected to the common mode terminal; wherein during the integration phase, the first parallel switch, the second parallel switch, and the first series switch are open, and the first ground switch is closed so that the input integration circuit charges the I first capacitances; during the gain phase, the first parallel switch, the second parallel switch, and the first series switch are closed, and the first ground switch is open, such that the portion of the first capacitance is connected in parallel and in series with the other portion of the first capacitance; A third parallel switch electrically connected between the first ends of adjacent ones of the partial second capacitances, a fourth parallel switch electrically connected between the second ends of adjacent ones of the partial second capacitances, a second ground switch electrically connected between the second ends of the partial second capacitances and the common mode terminal, a second series switch electrically connected between the second ends of the partial second capacitances and the first ends of the other partial second capacitances, the second ends of the other partial second capacitances being directly electrically connected to the common mode terminal; The third parallel switch, the fourth parallel switch and the second series switch are opened in the integration stage, the second grounding switch is closed so that the input integration circuit charges the I second capacitors, and the third parallel switch, the fourth parallel switch and the second series switch are closed in the gain stage, and the second grounding switch is opened so that part of the second capacitors are connected in parallel and connected in series with the other part of the second capacitors.
7. The incremental analog-to-digital converter of any one of claims 4-6 wherein the passive noise shaping circuit comprises: The sampling capacitor is configured to sample the kth high-order integrated voltage in a sampling stage to obtain a kth sampling voltage; And the integrating capacitors are configured to be charged through the kth high-order integrating voltage in the sampling stage to obtain a charging voltage, and are electrically connected with the sampling capacitors in the integrating stage after the sampling stage to passively integrate the kth sampling voltage based on the charging voltage to obtain the kth passive integrating voltage, and are electrically disconnected with the sampling capacitors in the gain stage to be electrically connected with the passive amplifying circuit so as to passively gain the kth passive integrating voltage by utilizing the kth gain voltage to obtain the kth high-order gain voltage.
8. The incremental analog-to-digital converter of claim 7 wherein the plurality of integrating capacitors are further configured to be connected in parallel between the positive output and the negative output of the input integrating circuit during the sampling phase for charging via the kth high-order integrating voltage, and to be connected in series between the passive amplifying circuit and the quantizing circuit during the gain phase for passively gain the kth passive integrating voltage with the kth gain voltage and for providing the kth high-order gain voltage to the quantizing circuit.
9. The incremental analog-to-digital converter of claim 8 wherein the sampling capacitance of the passive noise shaping circuit comprises a first sampling capacitance and a second sampling capacitance; The passive noise shaping circuit further comprises: the first integrating switches are respectively connected between the first ends of the integrating capacitors and the first ends of the first sampling capacitors; the second integrating switches are respectively connected between the second ends of the integrating capacitors and the first ends of the second sampling capacitors; wherein the first and second integrating switches are configured to be opened during the sampling phase and the gain phase and closed during the integrating phase, such that the plurality of integrating capacitances passively integrate the kth sampling voltage based on the charging voltage to obtain the kth passive integrating voltage.
10. The incremental analog-to-digital converter of claim 8 wherein the plurality of integrating capacitances comprises Q first integrating capacitances and Q second integrating capacitances; The passive noise shaping circuit further comprises: a first summing switch connected between adjacent ones of the Q first integrating capacitances; A second summing switch connected between adjacent ones of the Q second integrating capacitances; The first summing switch, the second summing switch, the first gain switch, the second gain switch are configured to be opened during the sampling phase and the integration phase, and to be closed during the gain phase such that the first integration capacitances are connected in series between a first end of the passive noise shaping circuit and a first end of the quantization circuit, and such that the second integration capacitances are connected in series between a second end of the passive noise shaping circuit and a second end of the quantization circuit, such that the Q first integration capacitances and the Q second integration capacitances passively gain a kth passive integration voltage via the kth gain voltage when the passive amplification circuit provides the kth gain voltage to the passive noise shaping circuit, to provide the kth high gain voltage to the quantization circuit.
11. The incremental analog-to-digital converter of any one of claims 1-6 wherein the input integrating circuit comprises an active integrator, an active transfer function of the active integrator having an attenuation coefficient in terms of noise shaping effect relative to a passive transfer function based on the passive amplifying circuit and the passive noise shaping circuit, the attenuation coefficient being less than or equal to 1/8; the predetermined amplification factor of the passive amplification circuit is greater than or equal to 1.875.
12. A signal processing method, applied to the incremental a/d converter according to any one of claims 1 to 11, comprising: The input integrating circuit generates a j-th low-order integrated voltage according to an input signal from a signal input end under the control of a j-1-th coarse quantization value in a j-th period of M1 periods, and generates a k-th high-order integrated voltage according to the input signal under the control of a k-1-th fine quantization value in a k-th period of M2 periods after the M1 periods, wherein j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k; The passive amplifying circuit obtains a kth gain voltage according to a kth high-order integral voltage in an integral stage of a kth period based on a preset amplifying coefficient; The passive noise shaping circuit performs passive integration on the kth high-order integrated voltage in the integration stage to obtain a kth passive integrated voltage, and is electrically connected with the passive amplifying circuit in the gain stage of the kth period so as to perform passive gain on the kth passive integrated voltage by using the kth gain voltage to obtain a kth high-order gain voltage; The quantization circuit quantizes M1 low-order integral voltages respectively in M1 periods to generate M1 coarse quantized values, and quantizes M2 high-order gain voltages respectively in M2 periods to generate M2 fine quantized values, wherein the fine quantized values have higher precision than the coarse quantized values.

Description

Incremental analog-to-digital converter based on passive noise shaping and signal processing method Technical Field The invention relates to the technical field of quantization, in particular to an incremental analog-to-digital converter based on passive noise shaping and a signal processing method. Background Analog-to-Digital Converter (ADC) may include nyquist Analog-to-digital converters and oversampling Analog-to-digital converters. For example, the oversampling analog-to-digital converter may comprise a delta-sigma analog-to-digital converter. In the fields of sensor interfaces, array image processing or digital voltmeters and other instruments and meters, the accuracy, the power consumption and the area of the analog-to-digital converter have strict requirements. The incremental analog-to-digital converter (INCREMENTAL ADC, IADC) can be better adapted to such multi-channel application scenarios. However, it is difficult for an incremental analog-to-digital converter to meet the requirements of high precision and low power consumption at the same time. Disclosure of Invention In view of the above, the present invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method. According to one aspect of the invention, an incremental analog-to-digital converter based on passive noise shaping is provided, comprising an input integrating circuit configured to generate a jth low-order integrated voltage according to an input signal from a signal input end under control of a jth coarse quantization value in an M1 period, and to generate a kth high-order integrated voltage according to the input signal in a kth period of M2 periods after the M1 period under control of a kth-1 fine quantization value, wherein j and k are integers greater than 1, M1 is an integer greater than or equal to j, M2 is an integer greater than or equal to k, a passive amplifying circuit configured to generate a kth gain voltage according to the kth high-order integrated voltage in an integrating period based on a predetermined amplification coefficient in the integrating period, a passive noise shaping circuit configured to passively integrate the kth high-order integrated voltage in the integrating period, and to generate a kth passive integrated voltage in the gain period in the k period, and to be electrically connected with the M1 fine quantization value in the M period, wherein M2 is an integer greater than or equal to k, and M2 is a quantized gain voltage in the M1 period, and M2 is quantized with a gain value in the gain value, and M2 is quantized in the gain quantization value. According to another aspect of the invention, a signal processing method is provided, and is applied to the incremental analog-to-digital converter, the signal processing method comprises the steps that an input integrating circuit generates a j-th low-bit integrating voltage according to an input signal from a signal input end in a j-th period of M1 periods under the control of a j-1-th coarse quantization value, generates a k-th high-bit integrating voltage according to the input signal in a k-th period of M2 periods after the M1 periods under the control of a k-1-th fine quantization value, wherein j and k are integers larger than 1, M1 is an integer larger than or equal to j, M2 is an integer larger than or equal to k, a passive amplifying circuit obtains a k-th gain voltage in an integrating period based on a preset amplifying coefficient, a passive noise shaping circuit performs passive integration on the k-th high-bit integrating voltage in the integrating period, generates a k-th high-bit integrating voltage in the gain period, is electrically connected with the passive amplifying circuit in the gain period of the k-th period, the passive amplifying circuit is used for generating a quantized gain value M2 in the M1-th high-bit quantization value relative to the M1-th high-bit quantization value, and the M2-bit quantization value is generated in the M1-th high-bit quantization value in the M1 periods respectively. According to an embodiment of the present invention, there is provided an incremental analog-to-digital converter based on passive noise shaping. In the incremental analog-to-digital converter, the input integrating circuit may generate M1 low-order integrated voltages for M1 cycles, respectively. The quantization circuit can quantize the M1 low-order integral voltages respectively to obtain M1 coarse quantized values. Thus, the first step of quantization can be completed. Further, in a kth period of the M2 periods, the input integrating circuit may generate a kth high-order integrated voltage according to the input signal under control of the kth-1 fine quantization value. Then, in the integration phase, the passive noise shaping circuit may passively integrate the kth high-order integrated voltage to obtain the kth passive integrated voltage. And, the passive amplification circ