CN-121645977-B - Input end transistor with built-in high-frequency cutoff ring and preparation method thereof

Abstract

The invention discloses an input end transistor with a built-in high-frequency cutoff ring and a preparation method thereof. The transistor comprises a substrate, an epitaxial layer and an insulating layer which are sequentially arranged from bottom to top, wherein a buried layer is arranged between the substrate and the epitaxial layer, a cylindrical first doped region is arranged in the epitaxial layer, an emitting region is arranged at the upper part in the first doped region, a capacitance medium is arranged at the upper part of the emitting region, the first doped region and the capacitance medium are led out through first metal and serve as a base electrode, the emitting region is led out through second metal and serve as an emitter electrode, a second doped region arranged at the outer side of the first doped region is arranged at the upper part in the epitaxial layer, a third doped region is arranged between the first doped region and the second doped region, the second doped region is led out through the third metal, a diffusion region is further arranged at the right side in the epitaxial layer, the diffusion region is connected with the buried layer and the insulating layer, a fourth doped region is arranged at the upper part in the diffusion region, and the fourth doped region is led out through fourth metal. The transistor has high integration level, strong anti-interference capability, small chip area and low cost.

Inventors

• SONG BIN
• DING YI

Assignees

• 杭州致善微电子科技有限公司

Dates

Publication Date

20260512

Application Date

20260205

Claims (6)

1. 1. The transistor is characterized by comprising a substrate, an epitaxial layer and an insulating layer which are sequentially arranged from bottom to top, wherein a buried layer is arranged between the substrate and the epitaxial layer, a cylindrical first doped region is arranged in the epitaxial layer, an emitting region is arranged at the upper part in the first doped region, a capacitance medium is arranged at the upper part of the emitting region, and the first doped region and the capacitance medium are led out through a first metal and serve as a base electrode; The upper part in the epitaxial layer is also provided with a second doped region arranged outside the first doped region, and a third doped region is arranged between the first doped region and the second doped region; The right side in the epitaxial layer is also provided with a diffusion region, the diffusion region is connected with the buried layer and the insulating layer, the upper part in the diffusion region is provided with a fourth doped region, and the fourth doped region is led out through fourth metal.
2. 2. The built-in high frequency cutoff ring input terminal transistor according to claim 1 wherein the first doped region is cylindrical, the emitter region is cylindrical, the capacitive medium is cylindrical, the second doped region is cylindrical, the third doped region is cylindrical, and the first doped region, the emitter region, the capacitive medium, the second doped region, and the third doped region are concentrically arranged.
3. 3. The built-in high frequency cut-off ring input terminal transistor according to claim 1, wherein the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an n+ emitter region, the second doped region is a P-type doped region, the diffusion region is an n+ diffusion region, and the fourth doped region is a P-doped region.
4. 4. The built-in high frequency cut-off ring input terminal transistor according to claim 1, wherein the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitter region is a p+ emitter region, the second doped region is an N-type doped region, the diffusion region is a p+ diffusion region, and the fourth doped region is an N-doped region.
5. 5. The input transistor with built-in high frequency cutoff ring according to any of claims 1-4 wherein the capacitive medium is silicon dioxide, silicon nitride or a composite of silicon dioxide and silicon nitride.
6. 6. A method of manufacturing an input-side transistor incorporating a high frequency cutoff ring as claimed in claim 1, comprising the steps of: (1) Forming an N-type buried layer on the P-type substrate through a pattern photomask and ion implantation of As; (2) Growing an N-type epitaxial layer with the thickness of 2-10um, wherein the doping concentration is 1e14cm -3 ~1e16cm -3 ; (3) Forming an N+ diffusion region on the N-type epitaxial layer through a pattern photomask and ion implantation of phosphorus; (4) Forming a first P-type region (5) and a second P-type region on the N-type epitaxial layer through a pattern photomask and implanting BF 2 + or 11 B; (5) Manufacturing an emitting region, a third doped region and a fourth doped region through a pattern photomask on the N-type epitaxial layer and ion implanting phosphorus or arsenic, and manufacturing a P-body region through ion implanting boron; (6) Performing thermal oxidation on the surface of silicon, and then depositing SiO 2 or Si 3 N 4 to manufacture an insulating layer; (7) Manufacturing a capacitor medium through a graph photomask and etching; (8) Manufacturing a lead hole layer through a pattern photomask and etching; (9) And manufacturing a metal lead-out layer, namely a first metal, a second metal, a third metal and a fourth metal.

Description

Input end transistor with built-in high-frequency cutoff ring and preparation method thereof Technical Field The invention relates to an input end transistor, in particular to an input end transistor with a built-in high-frequency cutoff ring and a preparation method thereof. Background In order to realize high-frequency cutoff, the prior art generally externally arranges a filter circuit, increases the cost and the separation devices, reduces the reliability, has unsatisfactory anti-interference effect, and also internally arranges a high-frequency cutoff ring, but the matched resistor is still externally arranged or independently arranged, thereby wasting the chip area, reducing the integration level and increasing the cost. Disclosure of Invention In order to solve the problems, the invention provides an input end transistor with a built-in high-frequency cutoff ring and a preparation method thereof. The invention provides a technical scheme that an input end transistor with a built-in high-frequency cutoff ring comprises a substrate, an epitaxial layer and an insulating layer which are sequentially arranged from bottom to top, wherein a buried layer is arranged between the substrate and the epitaxial layer, a cylindrical first doping region is arranged in the epitaxial layer, an emitting region is arranged at the upper part in the first doping region, a capacitance medium is arranged at the upper part of the emitting region, and the first doping region and the capacitance medium are led out through first metal and serve as a base electrode; The upper part in the epitaxial layer is also provided with a second doped region arranged outside the first doped region, and a third doped region is arranged between the first doped region and the second doped region; The right side in the epitaxial layer is also provided with a diffusion region, the diffusion region is connected with the buried layer and the insulating layer, the upper part in the diffusion region is provided with a fourth doped region, and the fourth doped region is led out through fourth metal. Further, the first doped region is cylindrical, the emitting region is cylindrical, the capacitance medium is cylindrical, the second doped region is cylindrical, the third doped region is cylindrical, and the first doped region, the emitting region, the capacitance medium, the second doped region and the third doped region are concentrically arranged. Further, the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an n+ emitter region, the second doped region is a P-type doped region, the diffusion region is an n+ diffusion region, and the fourth doped region is a P-doped region. Further, the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitting region is a P+ emitting region, the second doped region is an N-type doped region, the diffusion region is a P+ diffusion region, and the fourth doped region is an N-doped region. Further, the capacitance medium is silicon dioxide, silicon nitride or a composite material of silicon dioxide and silicon nitride. A preparation method of an input end transistor with a built-in high-frequency cutoff ring comprises the following steps: (1) Forming an N-type buried layer on the P-type substrate through a pattern photomask and ion implantation of As; (2) Growing an N-type epitaxial layer with the thickness of 2-10um, wherein the doping concentration is 1e14cm -3~1e16cm-3; (3) Forming an N+ diffusion region on the N-type epitaxial layer through a pattern photomask and ion implantation of phosphorus; (4) Forming a first P-type region (5) and a second P-type region on the N-type epitaxial layer through a pattern photomask and implanting BF2 or B11 ions; (5) Manufacturing an emitting region, a third doped region and a fourth doped region through a pattern photomask on the N-type epitaxial layer and ion implanting phosphorus or arsenic, and manufacturing a P-body region through ion implanting boron; (6) Performing thermal oxidation on the surface of silicon, and then depositing SiO 2 or Si 3N4 to manufacture an insulating layer; (7) Manufacturing a capacitor medium through a graph photomask and etching; (8) Manufacturing a lead hole layer through a pattern photomask and etching; (9) And manufacturing a metal lead-out layer, namely a first metal, a second metal, a third metal and a fourth metal. The cutoff frequency f T follows the formula f T =1/(2pi RC), where R is a resistor and C is a capacitor, and a designer can set different resistance values and capacitance values according to different application fields of the product, so as to realize different cutoff frequency requirements. The beneficial effects of the invention are as follows: the input