CN-121658302-B - SRAM (static random Access memory) storage calculation anti-radiation test method and system based on running state injection

CN121658302BCN 121658302 BCN121658302 BCN 121658302BCN-121658302-B

Abstract

The application relates to the technical field of SRAM (static random Access memory) storage anti-radiation test, and discloses an SRAM storage anti-radiation test method and system based on running state injection, wherein the method comprises the steps of system initialization, mapping preparation and time sequence base line establishment; the method comprises the steps of model quantification compiling, sensitivity analysis and physical bit candidate generation, running state injection plan generation and test case loading, running state execution, disturbance injection and synchronous monitoring acquisition, multi-source triggering, weight reading back and fault decoupling judgment, radiation resistance performance quantification evaluation, degradation curve construction and report output. The system corresponds to the method. The application constructs a hardware-in-loop running state injection and online evaluation technology, and realizes the technical problems of guidance, position-limited disturbance/equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping.

Inventors

DING DING
MA AO
TAN PEI
LONG PENG
ZHANG QIYI

Assignees

湖南工商大学

Dates

Publication Date: 20260508
Application Date: 20260205

Claims (10)

1. An SRAM (static random Access memory) storage anti-radiation test method based on running state injection is characterized by comprising the following steps: The system comprises a system initialization step, a mapping preparation step and a time sequence baseline establishment step, wherein the system initialization step is used for completing the system power-on self-checking and communication establishment step before the test is started, the tested SRAM type memory integrated chip working point configuration step, the logic-physical address mapping relation availability confirmation step, the time sequence calibration and delay compensation step of an injection/sampling link, the normal operation current fingerprint baseline establishment step and the key version and parameter tracing registration step, and the system enters a ready state for executable model mapping and sensitivity analysis after the completion step 10; The method comprises the steps of S20, performing model quantization compiling, sensitivity analysis and physical bit candidate generation, finishing fixed-point processing of a neural network model, organization mapping on a logic weight storage array, sensitivity calculation and sequencing of a quantized bit layer before test execution, and generating a physical sensitive bit candidate set for subsequent running state injection by combining a logic-physical mapping relation, wherein after S20, quantized model parameters, logic storage layout, sensitivity maps, the physical sensitive bit candidate set and confidence and version tracing information thereof are obtained, and input is provided for running state injection plan generation of S30; The method comprises the steps of S30, generating an operation state injection plan and loading test cases, wherein the operation state injection plan is used for generating an operation state injection plan for deterministic execution on the basis of obtaining a physical sensitive bit candidate set, and takes a physical injection position, an operation state window, a trigger condition, injection parameters, a sampling strategy and a readback strategy as core elements to form a structured test case set, and finishing loading and retrospective registration; S40, executing running state, disturbance injection and synchronous monitoring collection, wherein the data for executing disturbance injection on a designated physical position according to a running state injection plan and carrying out synchronous data collection and event association marking before and after an injection event under the running state that a tested SRAM type memory integrated chip executes a real reasoning/memory task; The method comprises the steps of S50, triggering multiple sources, weight reading back and fault decoupling judgment, wherein the method is used for triggering and executing a fault decoupling judgment flow based on calculation output abnormal evidence, current fingerprint abnormal evidence and reading back consistency evidence after each running state injection event; And S60, quantitatively evaluating the irradiation resistance, constructing a degradation curve and outputting a report, wherein the method is used for summarizing and counting injection event data, fault labels and evidence vectors formed in S40 to S50 to obtain occurrence characteristics of storage type soft errors, calculation type soft errors and single event latch under different injection conditions, constructing a mapping relation between injection intensity and calculation accuracy in an application layer to form a calculation accuracy degradation curve and a multidimensional irradiation resistance evaluation index set, generating a traceable evaluation report and outputting the traceable evaluation report.
2. The method for testing the storage and radiation resistance of the SRAM based on the running state injection according to claim 1, wherein the step S10 comprises the following steps: S101, carrying out power-on initialization, self-checking and basic communication handshake, namely, after a system is powered on, initiating a self-checking instruction and establishing a basic communication link; S102, loading the array structure parameters, the working voltage and the operating frequency configuration of the tested SRAM type integrated memory chip, and entering a preset working state; S103, loading and consistency checking of logic-physical address mapping, wherein the logic-physical address mapping relation is used for establishing and confirming the logic-physical address mapping relation required by subsequent injection and readback, specifically, loading a mapping table or mapping configuration data, and generating a mapping relation; S104, time sequence calibration and delay compensation loading of alignment of an operation state window are used for establishing an alignment relation between disturbance injection trigger time and the operation state window of the tested SRAM type integrated memory chip and determining delay compensation parameters of an injection link and a sampling link; S105, establishing a normal operation current fingerprint baseline and registering a threshold configuration, wherein the normal operation current fingerprint baseline is used for establishing a power domain current baseline fingerprint under the condition of no disturbance and is used as a reference input for subsequent abnormal identification and evidence fusion; And S106, setting an initialization parameter vector registration and system ready flag, and summarizing key configuration and verification results generated in S10 after the completion of S101 to S105 to form an initialization parameter vector and writing the initialization parameter vector.
3. The method for testing the radiation resistance of the SRAM memory based on the running state injection according to claim 1, wherein S20 comprises the following steps: S201, model fixed-point quantization and compiling processing is carried out on the neural network model to be tested, floating point weights are converted into fixed point weight representations, and quantization scales and bit width configuration are output; the method comprises the steps of S202, generating a logic storage layout and acquiring a physical bit coordinate set, wherein the logic storage layout is used for organizing the quantized logic weight into the logic storage layout mapped to an SRAM (static random access memory) storage array, and acquiring a corresponding physical bit coordinate set, so as to provide a foundation for subsequent directional injection and positioning; S203, calculating a level sensitivity index and generating a sensitivity map, wherein the level sensitivity index is used for calculating the influence degree of each logic level coordinate on the output correctness of the model, forming a sensitivity index, and generating a sensitivity ordering set and the sensitivity map; And S204, projection of a physical domain of the sensitivity map, candidate screening and retrospective registration, wherein the sensitivity map is projected from a logic domain to the physical domain, and a physical sensitivity bit candidate set is generated based on the mapping consistency coefficient and the screening threshold.
4. The method for testing the radiation resistance of the SRAM memory based on the running state injection according to claim 1, wherein S30 comprises: s301, screening an injection target set and generating an injection sequence, wherein the method comprises the steps of generating the injection target set based on a physical sensitive bit candidate set and a physical sensitive bit candidate item set and forming the injection sequence; s302, determining an operation state time window and constructing a triggering condition, wherein the operation state time window is used for determining the operation state injection time window of each injection target in the process of executing an reasoning/calculation task by the tested SRAM type integrated memory chip, and constructing a judged triggering condition; s303, generating and issuing a loading operation state injection plan, wherein the loading operation state injection plan is used for generating a structured operation state injection plan and issuing the structured operation state injection plan for subsequent execution; And S304, writing the injection plan and the configuration version, and carrying out versioning registration on the running state injection plan and the related configuration so that the data and the judgment result generated in the execution process can be in one-to-one correspondence with the specific plan, the specific threshold value, the specific sampling and the readback strategy.
5. The method for testing the radiation resistance of the SRAM memory based on the running state injection according to claim 1, wherein S40 comprises the following steps: S401, starting the running task of the tested SRAM type integrated memory and entering the running state monitoring, issuing a task starting instruction according to the configuration of the to-be-tested neural network task, coordinating the tested SRAM type integrated memory to enter a memory mode and executing an reasoning/memory task; s402, disturbance injection triggering and injection execution in an operation state window, wherein the disturbance injection triggering and injection execution in the operation state window comprises condition triggering, disturbance injection execution and injection event identification generation; S403, calculating synchronous acquisition and time calibration of output data and power domain transient data, wherein the synchronous acquisition and time alignment and event association storage of output and current transient before and after injection are included; S404, extracting current fingerprint characteristics, analyzing frequency spectrum and generating an abnormal candidate mark, wherein the current fingerprint characteristics, the frequency spectrum and the abnormal candidate mark comprise the characteristic representation of power domain transient current evidence and the abnormal candidate mark generation, and input is provided for the subsequent fault decoupling judgment; And S405, data buffer forwarding, event link registration and execution state updating, including package forwarding of injected event data, event index registration and execution state updating, and providing complete data and traceable links for subsequent fault judgment and evaluation.
6. The method for testing the radiation resistance of the SRAM memory based on the running state injection according to claim 1, wherein the step S50 comprises the following steps: s501, starting a multi-source abnormal trigger criterion calculation and judgment flow, wherein the multi-source abnormal quantification and judgment starting condition generation and traceable trigger record establishment facing to a single injection event are carried out; S502, running maintenance and readback control, namely entering a readback state and positioning a readback range, wherein the steps comprise determining the readback range from injection positioning to readback, generating a readback address list and establishing readback control, and providing an executable readback object for subsequent consistency verification; s503, weight readback and bitwise consistency check, extracting a bit flip set, including bitwise consistency check of readback data and reference data and extraction of the bit flip set, and providing direct evidence for single event upset type fault judgment; s504, outputting error evidence and current evidence to fuse to form a multi-source evidence vector, wherein the multi-source evidence vector comprises unified expression and archiving of functional level, electric level and storage level evidence under a single injection event, and structured input is provided for subsequent fault type judgment; S505, decoupling judgment of fault type and label output, including decoupling judgment of single event locking, single event turning and single event transient in a single injection closed loop, confidence output and protection action linkage, and establishing a traceable judgment evidence link.
7. The method for testing the radiation resistance of the SRAM memory based on the running state injection according to claim 1, wherein S60 comprises: s601, fault event statistics and incidence calculation, including statistics and incidence quantification of fault events in the overall and injection condition dimensions, and providing basic statistics for degradation curve construction; S602, calculating a correctness index and constructing a degradation curve, wherein the correctness index is used for constructing a mapping relation between injection intensity and calculation correctness and generating a calculation correctness degradation curve; S603, generating a multi-dimensional anti-radiation evaluation index and outputting a result, wherein the multi-dimensional anti-radiation evaluation index set is generated on the basis of a degradation curve and fault rate statistics and is used for representing the anti-radiation capability of the integrated memory chip in an operation state.
8. The method for testing the radiation resistance of the SRAM based on the running state injection according to claim 5, wherein the step S404 is specifically as follows: receive the first Sub-injection correlated current data logging For compensated current sequence The feature extraction and frequency domain/time frequency analysis comprises extracting time domain feature vector Extracting frequency domain or time-frequency characteristic vector And combined into a current feature vector , wherein, Is the first The characteristic vector of the current of the secondary injection, Is the first The time domain feature vector of the sub-injection, Is the first A frequency domain/time frequency characteristic vector of secondary injection; Vector the current characteristics Matching with the normal operation current fingerprint baseline characteristics established in the step S10, and calculating the fingerprint deviation degree Degree of fingerprint deviation Specifically, fingerprint deviation degree is defined as characteristic distance , wherein, For the normal operation current fingerprint baseline characteristic vector determined based on S10, Is a distance of two norms, Is the first The degree of fingerprint deviation of the secondary injection; Acquiring the current abnormality threshold as Generating a current abnormality candidate flag Is expressed as ; Will be 、、 And the fault judgment and evaluation processing is used for synchronously writing the fault judgment and evaluation processing after being associated with the injection event identification as an electrical grade evidence index.
9. The method for performing radiation-proof test on SRAM memory based on running state injection as claimed in claim 6, wherein S505 is based on multi-source evidence vector Latch-up risk indicator Readback flip set Performing fault type decoupling judgment and outputting fault labels Confidence of decision Comprising: acquiring a latch decision threshold as ; If it meets Then determine the failure tag as , wherein, Is the first The failure signature of the secondary injection event, Is a single particle latch label, does not satisfy And the read-back flip count satisfies Then determine the failure label as Wherein Is a storage type soft error label and is used for turning over a set As evidence of the positioning of the tag, when not satisfied And store-level evidence Simultaneously outputting the abnormal candidate mark to satisfy Then determine the failure label as Wherein For the calculation type soft error label, the fault is generated in the calculation path or transient simulation disturbance without causing the memory bit to flip, if 、 And is provided with Then it is determined that there is no fault label Wherein Indicating that no determinable fault was detected; Defining confidence This confidence is a normalized combination of evidence intensities The mathematical expression of (2) is: Wherein: for the confidence level, the value range is 0, 1; 、 And The weight coefficient is preset; The method comprises the steps of outputting an abnormal threshold value for a preset value; a preset current abnormality threshold value; Representing the read-back address list length; outputting an error measure; Is the degree of fingerprint deviation; is storage level evidence; When (when) When the protection control request is output, the protection action is executed, and the protection action mark and the fault label are written in an associated way Writing to form final decision record entry of single injection event, wherein the injection event identification , For the injection of the planned version identification, In order to inject the entry sequence number, In order to inject the physical bit coordinates, For triggering output time, multi-source evidence vector is , In order to output the error metric, In order to output the abnormality candidate flag, In order to be a degree of deviation of the fingerprint, As a current anomaly candidate flag, The count is flipped for read back.
10. An SRAM (static random Access memory) storage anti-radiation test system based on running state injection and an SRAM storage anti-radiation test method based on running state injection as claimed in any one of claims 1 to 9 is characterized by comprising an upper computer control subsystem (1), a real-time main control unit (2), an anti-radiation injection and monitoring interface module (3), an SRAM storage integrated chip (4) to be tested, a fault judgment and evaluation processing unit (5), an address conversion and physical mapping verification unit (6), a time sequence calibration and delay compensation unit (7), a current fingerprint feature extraction and spectrum analysis unit (8) and a test data and version tracing management unit (9), wherein the upper computer control subsystem (1) is responsible for test task planning and algorithm side processing, the real-time main control unit (2) is responsible for time sequence execution and trigger control, the anti-radiation injection and monitoring interface module (3) is responsible for disturbance injection and power state monitoring, the tested storage integrated chip (4) is used as a test object to execute in-storage internal calculation, the fault judgment and evaluation processing unit (5) carries out judgment and physical mapping verification of multi-source data, the conversion and physical mapping verification unit (6), the time sequence calibration and delay compensation unit (7) provides time sequence calibration and delay calibration logic protection unit (7) to support current coordinate comparison and test logic level (9) and test data comparison and test logic level tracing verification unit (9), and a transient state comparison and a test logic level comparison and a test level comparison result is provided for the test data and a test level comparison result, and a test result is provided by the test system Reproducible and traceable processes and results.

Description

SRAM (static random Access memory) storage calculation anti-radiation test method and system based on running state injection Technical Field The application relates to the technical field of SRAM (static random Access memory) storage anti-radiation test, in particular to an SRAM storage anti-radiation test method and system based on running state injection. Background The existing SRAM memory integrated chip anti-radiation test technology mainly comprises a static data retention test method and a pure software fault injection simulation method. The former needs to be carried out in a mode that the chip only maintains a memory state and does not carry out analog operation, and although static bit flip (SEU) of the memory cell can be accurately detected, the dynamic working states of the sense amplifier, the ADC and the bit line current convergence path cannot be activated because the test state is seriously disjointed from the 'running state' that the chip actually carries out neural network reasoning. The result is that the risk of transient interference (SET) and Single Event Locking (SEL) caused by radiation particles to an analog computing circuit and excited under dynamic current cannot be captured, so that the test coverage rate is low, and the fatal functional hidden trouble of a chip under the real dynamic computing force field is seriously missed. On the other hand, the fault injection method adopting pure software simulation can simulate error propagation at the algorithm level, but relies on an idealized digital fault model, and completely ignores the specific simulated nonlinear characteristics of the integrated memory chip and the charge sharing effect at the physical layout level. In addition, the existing simple dynamic test scheme generally directly adopts an ideal digital result as a comparison gold standard, and does not consider inherent quantization noise and process deviation of calculation in an analog memory. Due to the lack of an online calibration criterion based on undisturbed reference output and a current fingerprint baseline and the lack of hardware evidence such as weight readback consistency verification and the like for decoupling faults of 'storage' and 'calculation', the method has obvious defects in fault positioning accuracy and judgment accuracy, and is easy to misjudge inherent simulation calculation errors/noise as irradiation faults (high misjudgment rate), or can not distinguish whether a fault source is data inversion from a storage unit or transient deviation of an operation state calculation link. In summary, the prior art generally has the technical defects of static test mode, physical authenticity loss, failure mechanism uncoupling, high false positive rate of simulation noise, lack of guidance test for key weight and the like. These problems are particularly prominent when the integrated memory chip is applied to the fields of high-reliability aerospace and nuclear industry, and the popularization and application of the chip in the radiation-resistant reinforcement design verification, screening and in-orbit health evaluation are limited. Aiming at the technical defects, a novel technical scheme for testing the radiation resistance of the SRAM integrated memory chip based on running state injection is needed in the prior art. Disclosure of Invention The application aims to provide an SRAM (static random Access memory) storage anti-radiation test method and system based on running state injection, which are used for solving the technical problems of how to construct a hardware-in-loop running state injection and online evaluation technology in the running state process of executing a neural network reasoning task by an SRAM-CIM (static random Access memory) chip in the prior art, and realizing guidance and position-limited disturbance/equivalent radiation injection based on weight bit level sensitivity and logic-physical mapping. In order to achieve the above object, the present application provides a method for testing the storage and anti-radiation of an SRAM based on running state injection, comprising: The system comprises a system initialization step, a mapping preparation step and a time sequence baseline establishment step, wherein the system initialization step is used for completing the system power-on self-checking and communication establishment step before the test is started, the tested SRAM type memory integrated chip working point configuration step, the logic-physical address mapping relation availability confirmation step, the time sequence calibration and delay compensation step of an injection/sampling link, the normal operation current fingerprint baseline establishment step and the key version and parameter tracing registration step, and the system enters a ready state for executable model mapping and sensitivity analysis after the completion step 10; The method comprises the steps of S20, performing model quantization compiling, sensitivit