CN-121672408-B - Packaging substrate and preparation method thereof

CN121672408BCN 121672408 BCN121672408 BCN 121672408BCN-121672408-B

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging substrate and a preparation method thereof, wherein the packaging substrate comprises a substrate and two isolating rings which are isolated from each other; the substrate comprises a bonding surface and a bottom surface which are opposite to each other, the two isolation rings extend along the direction vertical to the substrate and penetrate through the bonding surface and the bottom surface, a middle movable cavity with the top surface lower than the bonding surface and a movable cavity ring surrounding the two isolation rings are defined on the bonding surface, the bonding surface at the periphery of the movable cavity ring comprises the bonding rings, the top of any isolation ring and the bonding surface surrounding the bonding surface are isolated by the anti-overflow isolation groove ring, the bonding surface surrounding the anti-overflow isolation groove ring comprises a bonding pad, and the adjacent anti-overflow isolation groove rings are communicated by the middle movable cavity. At least, the packaging substrate with excellent electrical isolation performance and good thermal matching can be provided, and signal crosstalk caused by overlarge parasitic capacitance is avoided while the vertical interconnection and extraction of multiple paths of independent signals are realized.

Inventors

ZHAO QIANCHENG
TANG YI
SUN ZHIYU
LIU JIAXU

Assignees

北京大学

Dates

Publication Date: 20260508
Application Date: 20260205

Claims (10)

1. The packaging substrate is characterized by comprising a getter layer, a substrate and two annular isolation rings which are isolated from each other; the substrate comprises bonding surfaces and bottom surfaces which are opposite to each other; The two annular isolation rings extend along the direction vertical to the substrate and penetrate through the bonding surface and the bottom surface, and the top surfaces of the two annular isolation rings are flush with the bonding surface; a middle movable cavity with the top surface lower than the bonding surface and a movable cavity ring surrounding the two annular isolation rings are defined on the bonding surface, wherein the bonding surface at the periphery of the movable cavity ring comprises a bonding ring; The top of any one of the two annular isolation rings is isolated from the surrounding bonding surface by an anti-overflow isolation groove ring, the bonding surface surrounded by the anti-overflow isolation groove ring comprises a bonding pad, the adjacent anti-overflow isolation groove rings are communicated by the middle movable cavity, and the movable cavity ring, the anti-overflow isolation groove ring and the middle movable cavity are synchronously prepared by etching the preset depth in the same process step; The getter layer is positioned on the bottom surface of the middle movable cavity and the bottom surface of the movable cavity ring, and is used for being activated in the eutectic bonding process so as to realize vacuum packaging.
2. The package substrate of claim 1, wherein the bonding ring and the bonding pad are prepared simultaneously in the same process step.
3. The package substrate of claim 1, wherein the bonding ring is eutectic bonded to the bonding surface and the bonding pad is eutectic bonded to the bonding surface.
4. The package substrate of claim 1, wherein an orthographic projection of the bonding pad on the bonding surface surrounded by the spacer ring is located within the bonding surface surrounded by the spacer ring.
5. The package substrate of any one of claims 1-4, wherein the substrate has a resistivity of 0.001 Ω -cm to 1 Ω -cm.
6. A method of manufacturing a package substrate, comprising: Providing a substrate; Forming a plurality of annular grooves in the front surface of the substrate, wherein the annular grooves are distributed at intervals along a first direction parallel to the top surface of the substrate; Adopting a target temperature and glass reflow process to treat a borophosphate glass sheet, filling dielectric material layers in the annular grooves, and thinning the front and back surfaces of the substrate after cooling and solidifying until the top and bottom surfaces of the dielectric material layers are exposed, wherein the front surface of the rest of the substrate forms a bonding surface of the substrate, and the back surface of the rest of the substrate forms the bottom surface of the substrate; Forming a first graphical photoresist layer covering the conductive layer after forming the conductive layer on the bonding surface, wherein the conductive layer comprises a bonding pad and a bonding ring; Etching the substrate to a preset depth based on the first graphical photoresist layer, and simultaneously obtaining a cavity ring and isolation rings, wherein the cavity ring comprises an anti-overflow isolation groove ring, a middle movable cavity and movable cavity rings surrounding the plurality of annular isolation rings, two isolation rings are arranged at intervals along the first direction through the middle movable cavity, the top of any isolation ring is isolated from a bonding surface surrounding the isolation ring through the anti-overflow isolation groove ring, the bonding pad is positioned on the bonding surface surrounding the anti-overflow isolation groove ring, the adjacent anti-overflow isolation groove rings are communicated through the middle movable cavity, and the bonding ring is positioned on the bonding surface at the periphery of the movable cavity ring; and forming a getter layer, wherein the getter layer is positioned on the bottom surface of the middle movable cavity and the bottom surface of the movable cavity ring, and the getter layer is used for being activated in the eutectic bonding process so as to realize vacuum packaging.
7. The method of manufacturing a package substrate of claim 6, wherein the first patterned photoresist layer comprises a first pattern defining the anti-overflow spacer ring and a second pattern defining the middle movable cavity, the movable cavity ring, the first pattern exposing a top surface of the spacer ring; etching the substrate based on the first patterned photoresist layer to obtain a cavity ring and an isolation ring at the same time, including: and etching the substrate to a preset depth by taking the first graphical photoresist layer as a mask plate, and simultaneously obtaining a cavity ring and an isolation ring with the preset depth.
8. The method of manufacturing a package substrate according to claim 6, wherein filling the plurality of annular trenches with the dielectric material layer at the target temperature comprises: Bonding the front surface of the substrate with a borophosphate glass sheet to obtain a bonding sheet; And carrying out heat treatment on the bonding sheet at the target temperature in a tube furnace, so that the molten borophosphate glass sheet fills a plurality of annular grooves, wherein the target temperature is 850-1000 ℃.
9. The method of manufacturing a package substrate according to claim 6, further comprising: After forming the cavity ring and the isolation ring, forming a second patterned photoresist layer covering the cavity ring, the isolation ring and the conductive layer, the second patterned photoresist layer including an opening pattern for defining a getter layer; Forming a getter material layer at least filling the opening pattern; and removing the second graphical photoresist layer and the getter material layer outside the opening pattern, wherein the rest getter material layer is used for forming the getter layer.
10. The method of manufacturing a package substrate according to claim 9, further comprising: Providing a MEMS device layer; And eutectic bonding the MEMS device layer and the conductive layer under preset process conditions, wherein the getter layer is activated during the eutectic bonding, and vacuum airtight packaging conditions are provided for the MEMS device layer.

Description

Packaging substrate and preparation method thereof Technical Field The disclosure relates to the technical field of semiconductor manufacturing, in particular to a packaging substrate and a preparation method thereof. Background In the manufacturing and packaging process of Micro Electro MECHANICAL SYSTEM, MEMS (Micro Electro) devices, wafer level packaging technology is one of key technologies for realizing miniaturization, high performance, high reliability and low-cost mass production of devices. Vertical interconnection of electrical signals is a core link for realizing three-dimensional integration and high-density packaging, and through silicon via (Through Silicon Via, TSV) technology is a main technical path for realizing vertical electrical extraction. However, the conventional TSV technology faces many challenges in multi-path electrical signal isolation, process complexity, thermal mismatch control, package air tightness, etc., and is prone to interface cracking or insulating layer failure, thereby reducing package yield and device reliability. Disclosure of Invention According to various embodiments of the present disclosure, a package substrate and a method for manufacturing the same are provided, which can at least provide a package substrate with excellent electrical isolation performance and good thermal matching, and avoid signal crosstalk caused by excessive parasitic capacitance while realizing vertical interconnection and extraction of multiple paths of independent signals. According to some embodiments, a first aspect of the disclosure provides a package substrate, which comprises a substrate and two isolation rings isolated from each other, wherein the substrate comprises a bonding surface and a bottom surface which are opposite to each other, the two isolation rings extend in a direction perpendicular to the substrate and penetrate through the bonding surface and the bottom surface, a middle movable cavity with a top surface lower than the bonding surface and a movable cavity ring surrounding the two isolation rings are defined on the bonding surface, the bonding surface at the periphery of the movable cavity ring comprises the bonding ring, the top of any isolation ring and the bonding surface surrounding the bonding surface are isolated by an anti-overflow isolation groove ring, the bonding surface surrounding the anti-overflow isolation groove ring comprises a bonding pad, and adjacent anti-overflow isolation groove rings are communicated by the middle movable cavity. The packaging substrate in the embodiment is characterized in that the isolation rings extend along the direction vertical to the substrate and penetrate through the bonding surface and the bottom surface of the substrate, a middle movable cavity with the top surface lower than the bonding surface and a movable cavity ring surrounding the two isolation rings are defined on the bonding surface of the substrate, wherein the top of any isolation ring is isolated from the bonding surface surrounding the isolation ring through an anti-overflow isolation groove ring in the two isolation rings, so that the top of the isolation ring is isolated from the adjacent bonding surface through the anti-overflow isolation groove ring, an isolation containing space is provided for the bonding metal in the subsequent melt flow, the thermal stress mismatch between the substrate and the isolation ring can be effectively reduced, the problem of poor electrical insulation can be effectively avoided, and the parasitic capacitance can be reduced while the electrical isolation performance is improved. The bonding surface surrounded by the anti-overflow isolation groove ring comprises a bonding pad, and the bonding surface on the periphery of the movable cavity ring comprises a bonding ring, so that signal crosstalk caused by overlarge parasitic capacitance is avoided while the vertical interconnection and extraction of multiple paths of independent signals are realized, and compared with a horizontal extraction scheme, the length of an interconnection signal line is reduced, and the anti-overflow isolation groove ring has a wide application prospect in the field of three-dimensional integration. Adjacent anti-overflow isolation groove rings are communicated through a middle movable cavity, and the movable cavity rings can circumferentially encircle the two isolation rings, so that vacuum packaging is facilitated. According to some embodiments, the movable cavity ring, the anti-overflow isolation groove ring and the middle movable cavity are prepared synchronously in the same process steps, so that the number of photomasks and the number of process steps for preparing the movable cavity ring, the anti-overflow isolation groove ring and the middle movable cavity are reduced, and the complexity and cost of a preparation process are reduced. According to some embodiments, the bonding ring and the bonding pad are prepared synchronously in the same