CN-121683666-B - Device and method for accelerating high-precision ADC data operation

CN121683666BCN 121683666 BCN121683666 BCN 121683666BCN-121683666-B

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a device and a method for accelerating high-precision ADC data operation, wherein the device comprises a bus, a data bus and a data bus, wherein the bus comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input-output mapping module, a register module and an algorithm accelerating core function module, wherein the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm accelerating core function module, and the register module comprises a configuration register, a plurality of operand registers and a configuration register. According to the invention, the address access request from the address bus is split into two parts, and the calculation input and output are selected through address mapping, so that the calculation result can be directly imported to the newly initiated calculation input end, the reading and writing of the processor to the operand register can be reduced, and the operation efficiency is improved.

Inventors

LI PEIXIN
LIANG XIANG
WANG ZHAOLONG
LIU YINCAI

Assignees

苏州领慧立芯科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260206

Claims (8)

1. An apparatus for accelerating high precision ADC data operations, comprising: a bus including an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input-output mapping module, a register module and an algorithm accelerating core function module; the address mapping logic module is used for splitting an address access request from the address bus into a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module; the register module comprises a configuration register related to the hardware algorithm accelerator, a plurality of operand registers for storing data and a configuration register for clearing the operand register data; The input-output mapping module is used for selecting the input and output of the algorithm called by the algorithm acceleration core function module according to the parameters and the information in the operation command each time, sending the value in the corresponding operand register module to the input end of the algorithm acceleration core function module, and sending the value of the output end of the algorithm acceleration core function module to the corresponding operand register when the algorithm acceleration core function module finishes calculation; the algorithm accelerating core function module is integrated with a plurality of algorithm core accelerating function units and is used for updating the calculation related parameter configuration of each algorithm core accelerating function unit according to the parameters and the operation command; The algorithm core acceleration function units comprise a multiplication and addition unit, a division unit and a cordic unit; when at least two operand registers are spliced, sign bits are automatically complemented for the spliced high-order operand registers when the spliced low-order operand registers are written.
2. The apparatus of claim 1, wherein each module within the hardware algorithm accelerator cooperates with a function implemented for one read operation from the address bus including selection and configuration updating of an algorithm, an arbitrary permutation and combination of an input and output of an algorithm acceleration core function module and the operand registers, and updating of the operand register data to reduce register read and write operations from bus redundancy.
3. The apparatus of claim 1, wherein the address mapping logic module performs a segmentation process on address information of one address access, uses a part of address bits located at a high level for operand register selection, and uses another part of address bits located at a low level for generating parameters and operations, thereby implementing one address access operation to read and write the register module and update and configure an algorithm acceleration core function module, and performs a calculation operation while selecting an algorithm type, so as to save a program space and improve peripheral execution efficiency; The base address value of the peripheral is stored as data in the memory in the program of the address mapping logic module, and each register under the peripheral is accessed by using offset address addressing, so that the program execution efficiency and the storage space are optimized; the address mapping logic module maps a plurality of registers during one bus write operation, splits high and low bits of bus data at the moment, writes the split high and low bits of bus data into the mapped registers respectively, and maps the registers during one bus read operation, wherein the bus data is a spliced result of the registers.
4. The apparatus of claim 1, wherein the hardware algorithm accelerator maps the operand registers through high order bits such that a program only stores an address corresponding to the operand register as a base address, parameters and operations as offset addresses after compiling is completed, reducing a memory space of the program and optimizing execution efficiency; When the hardware algorithm accelerator parameters and operations need to be updated frequently, updating the offset address by using a program only, and not storing the complete address information in a storage space; The hardware algorithm accelerator peripheral configuration comprises fixed point decimal related configuration, when the decimal function is selected, all input and output data are subjected to fixed point mapping according to configured decimal, the decimal precision is always kept unchanged during calculation, and further the problem of processing 24-bit or 32-bit data of the high-precision ADC is solved in a high-efficiency and low-power consumption mode, and the problem of overflow in high-precision ADC data processing is avoided.
5. The apparatus of claim 1, wherein some configuration information in the parameters and operation commands is stored in the configuration registers for a long period of time, and wherein when some configurations in an algorithm do not need to be changed each time the hardware algorithm accelerator peripheral is invoked, no parameter configuration update writes are required each time, thereby freeing up more address space for more parameter and operation mappings or algorithm function extensions; when the configuration information in the configuration register is used as the parameter of the algorithm module, only special bits in the parameter and the operation address are configured, so that more configuration mapping or operation mapping is flexibly performed by using an address space; After the hardware algorithm accelerator completes calculation, if part of operand registers are expected to be cleared to avoid interference with subsequent calculation, the corresponding registers are quickly reset by writing 1 clear bits into the operand registers in the configuration registers, so that the algorithm operation efficiency is improved; the configuration register also includes basic configuration information of the algorithm, and the selection is made by the operation in the address and the special bit in the parameter bit whether to use the configuration information in the configuration register.
6. A method for accelerating high precision ADC data operations performed in the apparatus of any one of claims 1-5, comprising: Judging parameters and operation addresses in an access request, selecting a configuration mode of an algorithm acceleration core function module, configuring an input-output mapping module, initiating operation by the algorithm acceleration core function module, and updating a state register after the operation is completed; And calling a hardware algorithm accelerator software flow, namely firstly calling an accelerator, judging whether an algorithm resides in configuration parameters or not, then judging whether the pre-writing of an operand register is finished or not, then writing final configuration parameters and operation addresses into the operand register, and finally completing calculation and calling.
7. The method of claim 6, wherein the determining the parameters and the operation addresses in the access request, selecting the configuration mode of the algorithm acceleration core function module, configuring the input-output mapping module, and finally initiating the operation by the algorithm acceleration core function module, and updating the status register after the operation is completed comprises: the hardware algorithm accelerator judges parameters and operation addresses in the received access request; If the parameters and the operation address are empty, mapping the parameters and the operation address to a register according to high bits, and writing data; If the parameter and the operation address are not null, selecting a configuration register or the parameter and the operation address to configure the algorithm acceleration core function module; configuring an input-output mapping module by utilizing the parameters and the operation address; the algorithm acceleration core function module initiates operation according to a configuration and calculation formula, updates a status flag bit, enters a busy state, pauses access operation of a bus to the operand register, and waits for completion of calculation; After the operation is completed, the status register is updated.
8. The method of claim 6, wherein first invoking the accelerator, determining whether the algorithm resides in the configuration parameters, then determining whether the operand registers are pre-written to completion, then writing the final configuration parameters and the operation address to the operand registers, and finally calculating completion, the completion of the invoking comprising: calling an accelerator, and judging whether an algorithm resides in configuration parameters or not; if the algorithm resides in the configuration parameters, writing the configuration register to configure the algorithm resides parameters; If the algorithm does not reside in the configuration parameters, pre-writing the algorithm operand register, wherein the parameters and the operation address are kept to be 0 in the pre-writing process until the pre-writing of the algorithm operand register is completed; Writing final configuration parameters and operation addresses to the operand registers; waiting for completion of calculation, or reading a flag bit to judge whether the calculation is completed, or reading an output result bus to be suspended; after the calculation is completed, the accelerator call is completed.

Description

Device and method for accelerating high-precision ADC data operation Technical Field The invention relates to the technical field of integrated circuit design, in particular to a device and a method for accelerating high-precision ADC data operation. Background Accelerating high-precision ADC data operation is an important subject in the technical field of data processing, wherein the high-precision ADC, the small-size MCU, the high-integration sensor and the integral collaborative cooperation of an analog front end are involved, and in the data operation process, the following technical problems generally exist: a) Low power consumption, small-sized MCUs and high integration sensors, analog front ends, etc. devices that integrate high precision ADCs typically do not use processors with hardware dividers and multiply-add instructions. In applications such as pressure sensors, calculations such as FFT, filtering, etc. typically do not have the ability to accelerate hardware for pressure temperature nonlinear calibration and compensation algorithms. However, its kernel itself has limited capability to handle complex computations. In order to improve the data processing efficiency of the high-precision ADC without remarkably increasing the power consumption and the chip area, the integrated algorithm accelerator is an important technical path. B) The low power consumption and small size MCU processor is usually an 8-bit computer, a 16-bit computer and a 32-bit computer, and maximally supports multiplication and addition and subtraction operations of 32-bit output results, when 24-bit or 32-bit ADC output data is processed, overflow problems are likely to occur to cause data errors, and although the overflow problems can be solved by reducing the data bit width through shifting, ADC precision is lost. While this problem can be solved by software re-asserting large bit width variables or converting the data to floating point (e.g., int64, double) calculations, significant performance, power consumption, and real-time costs are incurred. C) Due to limitations in low power consumption, small-sized MCUs on storage resources, instruction set capabilities, and power consumption budget. The related software algorithm of data processing is difficult to consider among the code size, the execution speed and the power consumption, and the application of the low-power consumption and small-size MCU in a high-precision ADC scene is restricted. With less hardware resource overhead, it is significant to efficiently solve the problem related to computation. D) The greater the complexity of the software algorithm calling the hardware algorithm accelerator, the higher the performance of the hardware algorithm accelerator, the higher the communication frequency between the processor and the hardware algorithm accelerator, and the more obvious the performance loss of the whole algorithm caused by the reading and writing of the register. For example, the multiplication and addition module accelerates the filter, the butterfly operation module accelerates the fast Fourier transform and other algorithms to accelerate the scene. Therefore, the efficient calling of the hardware algorithm accelerator has important significance. E) In MCU chip design, the integration difficulty and expansibility of peripheral modules directly influence the cost and design period of the product. For a hardware algorithm accelerator, when functions are added or extended, for example, algorithms are added, the complexity of system integration is not expected to be increased, and the expandability and compatibility of the system are affected. The hardware algorithm accelerator designed by the interface of the patent CN105988773a uses the low order address to map to the operand register and the high order address to map to the configuration selection, which makes it impossible to optimize the program space using offset addresses. The hardware algorithm accelerator designed by the interface of the patent CN105988773A of the invention needs to frequently adjust the input and output operand registers when the formula operation is complex, and the processor needs to frequently read and write the registers, thereby influencing the peripheral operation efficiency. When the hardware algorithm accelerator program designed by the interface of the patent CN105988773A of the invention performs calculation of 64-bit operand input, input data is spliced by 2 32-bit operand registers, and the operand registers are required to be written respectively to ensure correct input of sign bits. The hardware algorithm accelerator designed by the interface of the patent CN105988773A needs to initialize a plurality of operand registers when performing complex operation, and the complex operation is realized by writing the operand registers for a plurality of times. The hardware algorithm accelerator program designed by the interface of the patent CN105988773A needs to store the multi