CN-121685247-B - FPGA-based intelligent image processing system and method

CN121685247BCN 121685247 BCN121685247 BCN 121685247BCN-121685247-B

Abstract

The invention discloses an intelligent image processing system and method based on an FPGA, and relates to the technical field of image processing. The system comprises an intelligent interface adaptation module, a scene self-adaptive binding engine and an AHB bus control module, wherein the intelligent interface adaptation module is used for converting image data of different interfaces into video streams with uniform formats, the scene self-adaptive binding engine is used for dynamically determining the binding relation between the video streams and the processing modules and the data bit width of a video bus according to processing tasks and the states of the modules, and the AHB bus control module is used for configuring the bit width of the video bus according to decision making and sending configuration information to the processing modules. The invention realizes plug-and-play access of the multi-source heterogeneous image, dynamic intelligent reconstruction of the processing pipeline and on-line optimization of bus parameters, and remarkably improves the flexibility, resource utilization rate and overall performance of the system.

Inventors

FU TING
XUE YU
LIU HENGWEI
FENG CHENG
TIAN WENLEI
SU DINGHUA

Assignees

四川赛狄信息技术股份公司

Dates

Publication Date: 20260505
Application Date: 20260210

Claims (8)

1. An FPGA-based intelligent image processing system, comprising: The intelligent interface adaptation module is arranged at the entrance of the video bus and is configured to identify the interface type of at least one image data source and convert the image data from different interface types into a video data stream with a uniform format according to the identification result; The scene self-adaptive binding engine is configured to determine the binding relation between the video data stream and at least one image processing module according to at least one processing task to be executed and the working state of each image processing module in the FPGA, and determine the data bit width of the video bus; The system comprises a scene self-adaptive binding engine, an AHB bus control module, an image processing module, a video data stream and a video data stream, wherein the scene self-adaptive binding engine is in communication connection with the scene self-adaptive binding engine, and is configured to configure the data bit width of the video bus through the AHB bus based on the data bit width so that the video bus transmits the video data stream with the configured data bit width; The intelligent interface adaptation module comprises: A protocol feature acquisition unit configured to acquire data format features and timing features of the image data in real time; The interface type identification unit is configured to match the data format characteristics and the time sequence characteristics of the image data with a pre-stored characteristic template, call standard conversion logic corresponding to the characteristic template if the matching is successful, and generate temporary conversion logic of the image data according to the data format characteristics and the time sequence characteristics if the matching is failed; A protocol conversion unit configured to convert the image data into a video data stream of a unified format by the standard conversion logic or the temporary conversion logic; The scene adaptive binding engine includes: the state monitoring unit is configured to continuously monitor the data flow of the video bus and the working state of each image processing module, wherein the working state comprises the resource utilization rate and the processing queue length; the attribute archive stores the priority of each processing task, the resource consumption coefficient and the processing delay tolerance, and the processing function and performance index of each image processing module; The binding algorithm unit is configured to establish an algorithm model with constraint by taking the maximized system throughput, the minimized total processing delay and the balanced resource load as optimization targets, take the current monitored data flow, the working state of each image processing module and the data called from the attribute archive as the input of the algorithm model, and solve the optimal binding relation between the video data flow and at least one image processing module in a preset time window by adopting a built-in optimization algorithm.
2. The FPGA-based intelligent image processing system according to claim 1, wherein the interface type recognition unit includes: A timing analysis subunit configured to derive generation rules of line synchronization, field synchronization, and pixel clock according to timing characteristics of the image data when matching fails; a data analysis subunit configured to determine an arrangement order and a bit width of the pixel data according to the data format characteristics when the matching fails; and a logic generation subunit configured to generate the temporary conversion logic based on the generation rule and the arrangement order and bit width of the pixel data.
3. The FPGA-based intelligent image processing system according to claim 1, wherein said AHB bus control module is further configured to: Periodically reading operation state data from a state register of each image processing module through an AHB bus, wherein the operation state data comprises at least one of processing frame rate, resource occupancy rate and error mark; and feeding the running state data back to the scene self-adaptive binding engine so that the scene self-adaptive binding engine can update the working state of each image processing module.
4. The FPGA-based intelligent image processing system according to claim 1, wherein said configuration information includes an identifier of said video data stream, a processing function enable signal, and processing parameters; the identifier of the video data stream is used for indicating the video data stream to be processed by the image processing module, the processing function enabling signal is used for enabling or disabling the processing function of the image processing module, and the processing parameter is used for adjusting the operation behavior of the image processing module.
5. The FPGA-based intelligent image processing system of claim 1, further comprising a dynamic triggering and reconfiguration module configured to send a rebind request to the scene adaptive binding engine in response to a scene change event, a system state event, and/or an external instruction event, and trigger the AHB bus control module to update the configuration information based on a new binding relationship.
6. The FPGA-based intelligent image processing system according to claim 5, wherein said dynamic triggering and reconfiguration module comprises: a trigger condition monitor configured to continuously monitor a scene change event, a system status event, and/or an external instruction event; A hierarchical reconfiguration unit configured to select a reconfiguration class according to an event type, the reconfiguration class including a first reconfiguration class, a second reconfiguration class, and a third reconfiguration class; The first reconfiguration level triggers the AHB bus control module to update processing parameters in the configuration information, the second reconfiguration level triggers the adjustment of bit width of the video bus, and the third reconfiguration level triggers the scene adaptive binding engine to update the binding relation.
7. The FPGA-based intelligent image processing system of claim 1, wherein the video bus comprises a bit width configuration register, and wherein the AHB bus control module is further configured to write a bit width configuration value to the bit width configuration register via the AHB bus to adjust a data bit width of the video bus.
8. An FPGA-based intelligent image processing method, wherein the method is applied to the FPGA-based intelligent image processing system according to any one of claims 1 to 7, and includes: identifying interface types of at least one image data source, and converting image data from different interface types into a video data stream in a unified format according to the identification result; Determining a binding relation between the video data stream and at least one image processing module according to at least one processing task to be executed and the working state of each image processing module in the FPGA, and determining the data bit width of a video bus; Based on the data bit width, configuring the data bit width of the video bus through an AHB bus so that the video bus transmits the video data stream with the configured data bit width; And based on the binding relation, sending configuration information to the image processing module through an AHB bus so that the image processing module processes the video data stream based on the configuration information.

Description

FPGA-based intelligent image processing system and method Technical Field The invention relates to the technical field of image processing, in particular to an intelligent image processing system and method based on an FPGA. Background Existing FPGA-based image processing systems typically employ a fixed interface dedicated acquisition module architecture that is directly connected to a particular processing pipeline. The architecture has the obvious defects that firstly, the system cannot adaptively access image sources adopting different physical layer or link layer protocols, and hardware design needs to be customized for each interface, so that the system is complex to integrate, high in cost and poor in expansibility. And secondly, the binding relation between the image data stream and the processing module is solidified in the system design stage, and cannot be dynamically adjusted according to real-time task demands or system loads, so that the optimal scheduling and multiplexing of resources are difficult to realize. In addition, the bit width of the system bus is usually fixed, and when the high-resolution and high-frame-rate image data is processed, the clock frequency is often required to be increased to ensure the bandwidth, which brings great challenges to the timing convergence of the FPGA and limits the increase of the system performance. The problems cause that the traditional system has insufficient flexibility, low resource utilization rate and high operation and maintenance cost in the scenes of intelligent security, industrial vision, medical image and other multi-source input and dynamic requirements, and is difficult to meet the actual requirements of intelligent processing. Disclosure of Invention The invention provides an intelligent image processing system and method based on an FPGA (field programmable gate array), which are used for solving the technical problems of rigidification of interface adaptation, fixed binding of a processing flow and a module, incapability of dynamically adjusting bus bit width and dependence on manual intervention of system reconfiguration of the traditional FPGA image processing system. The invention is realized by the following technical scheme: in a first aspect of the present invention, there is provided an FPGA-based intelligent image processing system, comprising: The intelligent interface adaptation module is arranged at the entrance of the video bus and is configured to identify the interface type of at least one image data source and convert the image data from different interface types into a video data stream with a uniform format according to the identification result; The scene self-adaptive binding engine is configured to determine the binding relation between the video data stream and at least one image processing module according to at least one processing task to be executed and the working state of each image processing module in the FPGA, and determine the data bit width of the video bus; The system comprises a scene self-adaptive binding engine, an AHB bus control module, an image processing module and a video processing module, wherein the scene self-adaptive binding engine is in communication connection with the scene self-adaptive binding engine, the AHB bus control module is configured to configure the data bit width of the video bus through the AHB bus based on the data bit width so that the video bus can transmit the video data stream with the configured data bit width, and based on the binding relation, the configuration information is sent to the image processing module through the AHB bus so that the image processing module can process the video data stream based on the configuration information. Further, the intelligent interface adaptation module includes: A protocol feature acquisition unit configured to acquire data format features and timing features of the image data in real time; The interface type identification unit is configured to match the data format characteristics and the time sequence characteristics of the image data with a pre-stored characteristic template, call standard conversion logic corresponding to the characteristic template if the matching is successful, and generate temporary conversion logic of the image data according to the data format characteristics and the time sequence characteristics if the matching is failed; And a protocol conversion unit configured to convert the image data into a video data stream of a unified format by the standard conversion logic or the temporary conversion logic. Further, the interface type identifying unit includes: A timing analysis subunit configured to derive generation rules of line synchronization, field synchronization, and pixel clock according to timing characteristics of the image data when matching fails; a data analysis subunit configured to determine an arrangement order and a bit width of the pixel data according to the data format characteristics whe