CN-121687150-B - Memory device and electronic apparatus

CN121687150BCN 121687150 BCN121687150 BCN 121687150BCN-121687150-B

Abstract

The application provides a memory and an electronic device. The memory device comprises a memory array, an on-chip controller and a memory controller, wherein the memory array comprises a first memory area and a second memory area, the first memory area is used for storing normal data, the second memory area is used for storing metadata, the on-chip controller is configured to receive a first read-write command in a first mode, the first read-write command comprises a target data read-write command and a metadata read-write command which occur successively, the on-chip controller intercepts the metadata read-write command in the first mode and outputs the target data read-write command, and the memory array is configured to respond to the target data read-write command in the first mode and access the first memory area and the second memory area in parallel.

Inventors

LI HONGWEN
XIAO LEI
SUN JIANPENG

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260209

Claims (13)

1.A memory device, comprising: A storage array including a first storage area for storing normal data and a second storage area for storing metadata; the on-chip controller is configured to receive a first read-write command in a first mode, wherein the first read-write command comprises a target data read-write command and a metadata read-write command which appear successively, and intercept the metadata read-write command and output the target data read-write command in the first mode; Wherein the memory array is configured to access the first memory area and the second memory area in parallel in response to the target data read-write command in the first mode.
2. The memory device of claim 1, wherein the first memory region and the second memory region are laid out within the same memory portion.
3. The memory device of claim 2, wherein the first memory region comprises a plurality of first memory blocks and the second memory region comprises at least one second memory block.
4. The memory device of any one of claims 1 to 3, wherein accessing the first memory region and the second memory region in parallel includes the target data read-write command corresponding to a burst transfer, wherein the first memory region and the second memory region are accessed within a burst transfer.
5. The memory device of any one of claims 1 to 3, further comprising a data bus coupled between the on-chip controller and the memory array, wherein in the first mode, data transferred on the data bus during each read and write operation includes the normal data and the metadata in response to the target data read and write command.
6. The memory device of claim 1, wherein the on-chip controller comprises: a latch circuit configured to receive the first read-write command and delay the first read-write command to generate and output a delayed command; And a masking circuit receiving a target decoding signal and the delay command, wherein the target decoding signal has a first state if the delay command is obtained based on the metadata read-write command in the first mode, and has a second state if the delay command is obtained based on the target data read-write command in the first mode, the masking circuit being configured to mask the delay command in response to the target decoding signal having the first state, and output the delay command as the target data read-write command in response to the target decoding signal having the second state.
7. The memory device of claim 6, wherein the latch circuit comprises: the data input end of the D trigger receives the first read-write command, the output end of the D trigger outputs the delay command, and/or the shielding circuit comprises: A latch, a data input end of which receives the target decoding signal, a clock end of which receives the delay command and outputs the target decoding signal when the delay command is enabled; And one input end of the NOR gate is connected with the output end of the latch, the other input end of the NOR gate receives the inverted signal of the delay command, and the output end of the NOR gate is used for outputting the target data read-write command.
8. The memory device of claim 6, wherein the on-chip controller further comprises: A first decoding circuit configured to output the first read/write command to the latch circuit; and the second decoding circuit is used for outputting the target decoding signal to the shielding circuit.
9. The memory device of claim 1, wherein the on-chip controller is further configured to receive a second read-write command in a second mode, the second read-write command to instruct parallel storage or readout of normal data and metadata in the memory array, the second read-write command being output by the on-chip controller in the second mode; Wherein the memory array is further configured to access the first memory area and the second memory area in parallel in response to the second read-write command in the second mode.
10. The memory device of claim 9, wherein the second mode includes a first bit width mode in which the metadata that is accessed to the second memory area for single access has a first bit width or a second bit width mode in which the metadata that is accessed to the second memory area for single access has a second bit width, the first bit width being smaller than the second bit width.
11. The memory device of claim 1, wherein the memory device further comprises: A column decoder connected to the first memory area through a plurality of first column selection lines and connected to the second memory area through a plurality of second column selection lines; The accessing the first storage area and the second storage area in parallel in response to the target data read-write command includes: normal data is stored based on a first column address for selecting a plurality of the first column select lines and metadata is stored based on a second column address for selecting a plurality of the second column select lines, or the normal data is read based on the first column address and the metadata is read based on the second column address.
12. The memory device of claim 11, wherein the memory device is further configured to operate in a third mode in which the memory array is configured to store normal data based on the first column address for selecting a plurality of first column select lines and at least a portion of the second column select lines.
13. An electronic device comprising a memory device as claimed in any one of claims 1 to 12.

Description

Memory device and electronic apparatus Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a memory device and an electronic device. Background Semiconductor memories are classified into volatile memories such as static random access memory (SRAM, static Random Access Memory) or dynamic random access memory (DRAM, dynamic Random Access Memory) and nonvolatile memories such as flash memory, phase change RAM (PRAM, PCM-PHASE CHANGE MATERIAL Random Access Memory), magnetic RAM (MRAM, magnetoresistive Random Access Memory), resistive RAM (RRAM, RESISTIVE RANDOM-access memory) or ferroelectric RAM (FRAM, ferroelectric Random Access Memory). The volatile memory loses data stored therein when power is turned off, and the nonvolatile memory retains data stored therein even when power is turned off. DRAM memory is a common type of volatile memory. A DRAM memory is a type of memory in which a data writing operation is performed to the memory by storing charges in a capacitor of a memory cell, and a data reading operation is performed to the memory by reading charges in the capacitor of the memory cell. With the development of semiconductor technology, the integration level of DRAM is higher and higher, and the possibility of data errors during data read operations or data write operations is also increased. Disclosure of Invention The application provides a memory device and an electronic device, which are at least beneficial to improving the performance of the memory device. The application provides a storage device which comprises a storage array, an on-chip controller and a storage array, wherein the storage array comprises a first storage area and a second storage area, the first storage area is used for storing normal data, the second storage area is used for storing metadata, the on-chip controller is configured to receive a first read-write command in a first mode, the first read-write command comprises a target data read-write command and a metadata read-write command which occur successively, the on-chip controller intercepts the metadata read-write command in the first mode and outputs the target data read-write command, and the storage array is configured to respond to the target data read-write command in the first mode and access the first storage area and the second storage area in parallel. In addition, the first storage area and the second storage area are laid out in the same storage section. In addition, the first memory area includes a plurality of first memory blocks, and the second memory area includes at least one second memory block. In addition, accessing the first memory area and the second memory area in parallel includes the target data read-write command corresponding to a burst transfer, wherein the first memory area and the second memory area are accessed within a burst transfer. In addition, the memory device further includes a data bus coupled between the on-chip controller and the memory array, wherein, in the first mode, data transmitted on the data bus includes the normal data and the metadata during each read/write operation in response to the target data read/write command. In addition, the on-chip control includes a latch circuit configured to receive the first read-write command and to delay the first read-write command to generate and output a delayed command, a mask circuit to receive a target decode signal having a first state if the delayed command is obtained based on the metadata read-write command in the first mode and the delayed command having a second state if the delayed command is obtained based on the target data read-write command, and to output the delayed command as the target data read-write command in response to the target decode signal having the second state. In addition, the latch circuit comprises a D trigger, a NOR gate and an output end, wherein the data input end of the D trigger receives the first read-write command, the output end of the D trigger outputs the delay command, and/or the mask circuit comprises a latch, the data input end of the latch receives the target decoding signal, the clock end of the latch receives the delay command and outputs the target decoding signal when the delay command is enabled, one input end of the NOR gate is connected with the output end of the latch, the other input end of the NOR gate receives the inversion signal of the delay command, and the output end of the NOR gate is used for outputting the target data read-write command. In addition, the on-chip controller further comprises a first decoding circuit for outputting the first read-write command to the latch circuit, and a second decoding circuit for outputting the target decoding signal to the shielding circuit. In addition, the on-chip controller is further configured to receive a second read-write command for instructing parallel storage or readout of normal data and metadata in the storage array in