CN-121690196-B - Eye pattern data synchronizing circuit and method, serial-parallel converter receiving end

CN121690196BCN 121690196 BCN121690196 BCN 121690196BCN-121690196-B

Abstract

The invention discloses an eye pattern data synchronizing circuit and method and a serial-parallel converter receiving end, belonging to the technical field of high-speed serial data communication; the circuit comprises a calibration signal generating module for generating a phase calibration signal according to the phase difference between a data sampling signal and an offset sampling signal, two registers for outputting the offset sampling signal and a front offset sampling signal and a rear offset sampling signal respectively, wherein the front offset sampling signal and the rear offset sampling signal are obtained by outputting the offset sampling signal in advance/delayed by half a bit period, and a selection output module for selecting the offset sampling signal or the front offset sampling signal and the rear offset sampling signal as the synchronized offset sampling signal according to the phase calibration signal so as to enable the synchronized offset sampling signal and the data sampling signal to be in the same bit period. The invention has wide application range, higher synchronization precision and better dynamic property.

Inventors

WEI NING
JIA HONGYI
WEI QIN

Assignees

西安智多晶微电子有限公司

Dates

Publication Date: 20260508
Application Date: 20260212

Claims (10)

1. The eye pattern data synchronizing circuit is characterized by comprising a calibration signal generating module, a first register, a second register and a selection output module; The calibration signal generation module is used for generating a phase calibration signal according to the phase difference of a data sampling signal and an offset sampling signal, wherein the phase calibration signal is used for indicating the magnitude relation of the phase difference and a half bit period of the offset sampling signal; one of the first register and the second register is used for outputting an offset sampling signal, and the other is used for outputting the offset sampling signal in advance/delay half a bit period to obtain a front offset sampling signal and a rear offset sampling signal; The selection output module is used for selecting the offset sampling signal or the front/rear offset sampling signal as the synchronized offset sampling signal to be output according to the phase calibration signal so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; The first input end and the second input end of the selection output module are respectively connected with the output ends of the first register and the second register, and the signal input end of the selection output module is connected with the output end of the calibration signal generation module.
2. The eye pattern data synchronizing circuit of claim 1, wherein the calibration signal generating module comprises an auto-calibration module, a first inverter, a first data selector, a second inverter; The automatic calibration module is used for automatically generating a first phase calibration signal according to the phase difference; the first phase inverter is used for carrying out phase inversion processing on a preset phase difference indicating signal to obtain a second phase calibration signal; the first data selector is used for selecting the first phase calibration signal/the second phase calibration signal according to a calibration mode selection signal, and the second inverter is used for inverting the selected first phase calibration signal/second phase calibration signal and outputting the inverted first phase calibration signal/second phase calibration signal as the phase calibration signal; the output end of the automatic calibration module is connected with the I1 input end of the first data selector, the I0 input end of the first data selector is connected with the output end of the first phase inverter, the signal input end of the first data selector inputs the calibration mode selection signal, and the output end of the first data selector is connected with the input end of the second phase inverter.
3. The eye diagram data synchronization circuit of claim 2, wherein the auto-calibration module comprises an exclusive-or gate, a transmission gate, a capacitor, a nand gate, a third inverter, a third register; The first to third input ends of the exclusive-OR gate are respectively used as the first to third input ends of the automatic calibration module, the data clock signal after frequency division, the offset clock signal after frequency division and the calibration enabling signal are sequentially input, and the output end is connected with the input end of the transmission gate; The output end of the transmission gate and the first input end of the NAND gate are connected with one end of the capacitor, and the other end of the capacitor is grounded; The second input end of the NAND gate inputs the calibration enabling signal, and the output end of the NAND gate is connected with the input end of the third inverter; The output end of the third inverter is connected with the data input end of the third register; the output end of the third register is used as the output end of the automatic calibration module.
4. The eye pattern data synchronizing circuit according to claim 2, wherein the offset sampling signal is input to the data input terminals of the first and second registers, the first and second clock signals having opposite phases are input to the clock input terminals, respectively, the first and second clock signals are in the same frequency shape as the frequency-divided offset clock signal, and the offset clock signal is the sampling clock signal of the offset sampler.
5. The eye pattern data synchronization circuit of claim 4, wherein the register for outputting the offset sampling signal is determined based on the positive and negative of the phase difference and the effective sampling edges of the first and second registers.
6. The eye pattern data synchronization circuit of claim 5, wherein if the effective sampling edges of the first and second registers are both rising edges, the second register is configured to output the offset sampling signal when the phase difference is positive, and the first register is configured to output the offset sampling signal when the phase difference is negative; And if the effective sampling edges of the first register and the second register are both falling edges, the first register is used for outputting the offset sampling signal when the phase difference is positive, and the second register is used for outputting the offset sampling signal when the phase difference is negative.
7. The eye pattern data synchronization circuit of claim 1, wherein the select output module comprises a second data selector, a fourth inverter; The second data selector is configured to select the offset sampling signal or the pre/post offset sampling signal according to the phase calibration signal, and the fourth inverter is configured to invert and output the selected offset sampling signal or the pre/post offset sampling signal.
8. The eye pattern data synchronization circuit of claim 1, wherein the selection output module selects the pre/post offset sampling signal if the absolute value of the phase difference is greater than or equal to half a bit period, and the selection output module selects the offset sampling signal if the absolute value of the phase difference is less than half a bit period.
9. An eye data synchronization method, applied to the eye data synchronization circuit of any one of claims 1-8, comprising: generating a phase calibration signal according to a phase difference between a data sampling signal and an offset sampling signal, wherein the phase calibration signal is used for indicating a magnitude relation between the phase difference and a half bit period of the offset sampling signal; And selecting an offset sampling signal or a front/rear offset sampling signal as a synchronized offset sampling signal to be output according to the phase calibration signal so as to enable the synchronized offset sampling signal and the data sampling signal to be in the same bit period, wherein the front/rear offset sampling signal is obtained by outputting the offset sampling signal in advance/delay of half a bit period.
10. The receiving end of the serial-parallel converter is characterized by comprising a joint equalization module, a data sampler, an offset sampler, an eye pattern data synchronization circuit, an exclusive-OR gate and an error counter according to any one of claims 1-8; The combined equalization module is used for performing equalization processing on an input signal to obtain an equalization signal, the data sampler is used for sampling the equalization signal at the center of an eye diagram to obtain a data sampling signal, the offset sampler is used for sampling the equalization signal at the offset center position of the eye diagram to obtain an offset sampling signal, the eye diagram data synchronization circuit is used for performing synchronization processing on the offset sampling signal to obtain a synchronized offset sampling signal, the exclusive-nor gate is used for performing exclusive-nor operation on the synchronized offset sampling signal and the data sampling signal, and the error counter is used for performing error counting according to an exclusive-nor operation result to calculate an error rate.

Description

Eye pattern data synchronizing circuit and method, serial-parallel converter receiving end Technical Field The invention belongs to the technical field of high-speed serial data communication, and particularly relates to an eye pattern data synchronizing circuit and method and a serial-parallel converter receiving end. Background With the rapid development of technologies such as data centers, high-performance computing and 5G communication, the requirements on the data transmission rate between chips are increasingly increased. Serializer/Deserializer (SerDes) has been advancing to 112Gbps and higher in data transmission rate as a core technology for realizing high-speed interconnection. At such high rates, signal integrity presents significant challenges, including severe intersymbol interference, clock jitter, and channel loss. To overcome these challenges and ensure extremely low bit error rates, modern SerDes receivers typically employ a system architecture that combines a data sampler-based decision feedback equalization technique with an offset sampler-based adaptive equalization technique. The circuit has the advantages that the requirement on the working speed of the circuit is remarkably reduced, so that better performance, lower power consumption and higher reliability are realized in a high-speed scene. Bit error rate detection is a critical function in performing such system performance assessment and on-line monitoring. Conventional bit error rate detection methods are implemented by comparing the data recovered by the data sampler with known or expected data patterns. However, this method has an inherent problem in that it can only detect whether the data sampler itself is erroneous, but cannot effectively evaluate degradation of the equalization system performance caused by inaccuracy of the phase of the offset sampler. If the sampling phase of the offset sampler is not exactly aligned to the edge of the data eye, then the equalizer adaptation based on its output will be sub-optimal and possibly even erroneous. This will lead to a degradation of the equalization effect of the whole receiving end, and the actual system performance (such as the system level bit error rate) is far worse than the bit error rate measured based on the data sampler, forming a performance misjudgment. For this purpose, the offset sampler may be calibrated using the currently popular fixed delay line calibration method. The method attempts to make the clock paths of the data sampler and the offset sampler have a fixed delay difference through analog circuit design or layout matching in the chip design stage. At chip power up, the phase relationship between the two is roughly set by a simple calibration sequence (e.g., scanning a fixed delay code). However, this method cannot adapt to process, voltage and temperature variations, lacks dynamics and has limited accuracy. Disclosure of Invention The embodiment of the invention provides an eye pattern data synchronizing circuit and method and a serial-parallel converter receiving end, which can solve the technical problems. In a first aspect, the embodiment of the invention provides an eye pattern data synchronizing circuit, which comprises a calibration signal generating module, a first register, a second register and a selection output module; The calibration signal generation module is used for generating a phase calibration signal according to the phase difference of a data sampling signal and an offset sampling signal, wherein the phase calibration signal is used for indicating the magnitude relation of the phase difference and a half bit period of the offset sampling signal; one of the first register and the second register is used for outputting an offset sampling signal, and the other is used for outputting the offset sampling signal in advance/delay half a bit period to obtain a front offset sampling signal and a rear offset sampling signal; The selection output module is used for selecting the offset sampling signal or the front/rear offset sampling signal as the synchronized offset sampling signal to be output according to the phase calibration signal so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; The first input end and the second input end of the selection output module are respectively connected with the output ends of the first register and the second register, and the signal input end is connected with the output end of the calibration signal generation module. In a second aspect, an embodiment of the present invention provides an eye pattern data synchronization method, which is applied to the eye pattern data synchronization circuit in the first aspect, and the method includes: generating a phase calibration signal according to a phase difference between a data sampling signal and an offset sampling signal, wherein the phase calibration signal is used for indicating a magnitude relation between th