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CN-121690204-B - Comparator noise estimation method of successive approximation type analog-to-digital converter

CN121690204BCN 121690204 BCN121690204 BCN 121690204BCN-121690204-B

Abstract

The application relates to the technical field of integrated circuits and discloses a comparator noise estimation method of a successive approximation type analog-to-digital converter, which comprises the steps of charging a first capacitor array and a second capacitor array, and respectively connecting each capacitor in the first capacitor array and the second capacitor array with positive reference voltage and negative reference voltage; the method comprises the steps of connecting the lowest-order capacitors in a first capacitor array and a second capacitor array with negative reference voltage and positive reference voltage respectively, comparing the lowest-order capacitors in the first capacitor array and the second capacitor array with negative reference voltage and positive reference voltage respectively, calculating a first codeword according to a comparison result by a comparator, charging the first capacitor array and the second capacitor array, connecting each capacitor in the first capacitor array and the second capacitor array with negative reference voltage and positive reference voltage respectively, connecting the lowest-order capacitors in the first capacitor array and the second capacitor array with positive reference voltage and negative reference voltage respectively, comparing the lowest-order capacitors in the first capacitor array and the second capacitor array with the comparator for multiple times, calculating a second codeword according to the comparison result, obtaining probability values of normal distribution of noise of the comparator according to the first codeword and the second codeword, and determining corresponding standard deviation. The application can realize the on-chip automatic estimation of the noise of the comparator.

Inventors

  • Request for anonymity

Assignees

  • 上海启鸣芯半导体技术有限公司

Dates

Publication Date
20260512
Application Date
20260210

Claims (9)

  1. 1. A method of estimating comparator noise of a successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter comprising a first capacitor array, a second capacitor array, a comparator, and a logic control circuit, a top plate of each capacitor in the first capacitor array being connected to a negative input of the comparator and to a common mode voltage via a sampling switch, a top plate of each capacitor in the second capacitor array being connected to a positive input of the comparator and to the common mode voltage via a sampling switch, an output of the comparator being coupled to the logic control circuit, the logic control circuit determining a digital codeword from an output of the comparator to control a positive reference voltage or a negative reference voltage, respectively, a bottom plate of each capacitor in the first capacitor array and the second capacitor array, the method comprising the steps of: The sampling switch is turned on, the first capacitor array and the second capacitor array are charged through the common mode level, the bottom electrode plate of each capacitor in the first capacitor array is connected with the positive reference voltage, and the bottom electrode plate of each capacitor in the second capacitor array is connected with the negative reference voltage; the sampling switch is disconnected, the bottom electrode plate of the lowest-order capacitor in the first capacitor array is connected with the negative reference voltage, the bottom electrode plate of the lowest-order capacitor in the second capacitor array is connected with the positive reference voltage, the logic control circuit controls the comparator to conduct multiple comparisons and output comparison results, and a first codeword is calculated according to the comparison results; the sampling switch is turned on, the first capacitor array and the second capacitor array are charged through the common mode level, the bottom electrode plate of each capacitor in the first capacitor array is connected with the negative reference voltage, and the bottom electrode plate of each capacitor in the second capacitor array is connected with the positive reference voltage; Disconnecting the sampling switch, connecting the bottom plate of the lowest capacitance in the first capacitance array with the positive reference voltage, connecting the bottom plate of the lowest capacitance in the second capacitance array with the negative reference voltage, controlling the comparator to compare for multiple times and output a comparison result, and calculating a second codeword according to the comparison result, and Subtracting the first codeword from the second codeword and dividing the first codeword by 2 to obtain a probability value of the normal distribution of the comparator noise corresponding to the capacitor array unit voltage, and determining a standard deviation of the normal distribution of the comparator noise according to the probability value.
  2. 2. The method of claim 1, wherein the successive approximation analog-to-digital converter further comprises an estimation circuit comprising a flip-flop, a first adder, a divider, a counter, a second adder, and a look-up table circuit; The counter records the comparison times of the comparator, the trigger receives the comparison result of each comparison of the comparator, the first adder accumulates the comparison results of the comparator for a plurality of times and obtains an accumulated result, the divider calculates the first codeword and the second codeword according to the accumulated result and the comparison times, the second adder subtracts the first codeword from the second codeword and divides the second codeword by 2 to obtain a probability value of the comparator noise corresponding to a voltage value generated by the turnover of the first capacitor array and the second capacitor array, and the lookup table circuit obtains a standard deviation of the normal distribution of the comparator noise from a standard normal distribution stored in the lookup table circuit according to the probability value and the corresponding voltage value.
  3. 3. The method of claim 2, wherein the logic control circuit includes a clock generation circuit that generates a comparison clock signal to the comparator and the counter, the comparator performing a plurality of comparisons based on the comparison clock signal, the counter counting based on the comparison clock signal.
  4. 4. The method of claim 3, wherein the clock generation circuit generates a sampling clock signal that controls on/off of the sampling switch, the sampling switch is turned on when the sampling clock signal is high, the sampling switch is turned off when the sampling clock signal is low, and the clock generation circuit generates the comparison clock signal.
  5. 5. The method of comparator noise estimation of a successive approximation analog-to-digital converter of claim 2, wherein the flip-flop is an SR latch.
  6. 6. The method of estimating the comparator noise of a successive approximation type analog-to-digital converter according to claim 1, wherein the number of comparisons made by the comparator is 4 to 8.
  7. 7. The method of comparator noise estimation of a successive approximation analog-to-digital converter of claim 1, wherein the first capacitor array and the second capacitor array each comprise a plurality of bits of capacitance.
  8. 8. The method of claim 1, wherein bottom plates of each capacitor in the first capacitor array and the second capacitor array are each connected to a positive reference voltage and a negative reference voltage by a single pole double throw switch.
  9. 9. A successive approximation analog-to-digital converter comprising a first capacitor array, a second capacitor array, a comparator, and a logic control circuit, a top plate of each capacitor in the first capacitor array being connected to a common mode voltage and a negative input of the comparator and to the common mode voltage through a sampling switch, a top plate of each capacitor in the second capacitor array being connected to the common mode voltage and a positive input of the comparator and to the common mode voltage through a sampling switch, an output of the comparator being coupled to the logic control circuit, the logic control circuit determining a digital codeword from an output of the comparator to control a positive reference voltage or a negative reference voltage, respectively, a bottom plate of each capacitor in the first capacitor array and the second capacitor array, the successive approximation analog-to-digital converter further comprising: The logic control circuit charges the first capacitor array and the second capacitor array by controlling the sampling switch to enable the common mode level, the bottom electrode plate of each capacitor in the first capacitor array is connected with the positive reference voltage, the bottom electrode plate of each capacitor in the second capacitor array is connected with the negative reference voltage, then the bottom electrode plate of the lowest capacitor in the first capacitor array is connected with the negative reference voltage, the bottom electrode plate of the lowest capacitor in the second capacitor array is connected with the positive reference voltage, the logic control circuit controls the comparator to conduct multiple comparisons and output comparison results, and the noise estimation circuit calculates a first codeword according to the comparison results; the logic control circuit charges the first capacitor array and the second capacitor array by controlling the sampling switch to enable the common mode level, the bottom electrode plate of each capacitor in the first capacitor array is connected with the negative reference voltage, the bottom electrode plate of each capacitor in the second capacitor array is connected with the positive reference voltage, then the bottom electrode plate of the lowest capacitor in the first capacitor array is connected with the positive reference voltage, the bottom electrode plate of the lowest capacitor in the second capacitor array is connected with the negative reference voltage, the logic control circuit controls the comparator to conduct multiple comparisons and output comparison results, and the noise estimation circuit calculates a second codeword according to the comparison results; The noise estimation circuit subtracts the first codeword from the second codeword and divides the second codeword by 2 to obtain a probability value of a normal distribution of the comparator noise corresponding to the capacitor array unit voltage, and determines a standard deviation of the normal distribution of the comparator noise according to the probability value.

Description

Comparator noise estimation method of successive approximation type analog-to-digital converter Technical Field The present application relates to the field of integrated circuits, and in particular, to a method for estimating noise of a comparator of a successive approximation type analog-to-digital converter. Background In digital signal processing and electronic systems, it is often necessary to convert analog signals to digital signals for processing and storage by digital circuitry. Successive approximation analog-to-digital converters (Successive Approximation Register Analog to Digital Converter, SAR ADCs) are widely used due to their modest performance, low power consumption, and relatively simple structure. The main sources of noise in the successive approximation type analog-to-digital converter are the noise of the sampling switch, the comparator noise and the quantization noise. The comparator plays a critical decision role in each conversion of the SAR ADC. The higher the resolution of the SAR ADC, the higher the accuracy requirement on the comparator, and the accuracy of the output directly determines the accuracy of the SAR ADC conversion result. To explore the effect of comparator noise on SAR ADC performance, it is often necessary to estimate the magnitude of the comparator noise. The current method for estimating the noise of the comparator is to simulate the comparator circuit by using professional Electronic Design Automation (EDA) software, introduce random variation of device parameters in the simulation, and run the simulation for multiple times to obtain statistical distribution of the noise so as to obtain noise analysis and statistical results. In the prior art, the noise voltage of the comparator is determined through simulation, however, the actually produced chips are affected by factors such as temperature, process deviation and the like, and simulation data are not necessarily suitable for each chip. Therefore, the prior art has limited application range in engineering. In another scheme, zero level is input to the ADC by shorting the input end of the ADC, and the output of the SAR ADC is counted by directly using a histogram at the moment, so that the noise level of the SAR ADC can be obtained. And shorting the differential input end of the SAR ADC to a common mode voltage, sampling and quantizing the SAR ADC, wherein the output of each quantized SAR ADC is one sample, and then collecting a plurality of samples. Since there is no actual signal input, any variation can be attributed to internal noise, including comparator noise. The noise level can be estimated by statistically analyzing the distribution of these samples. The noise obtained by the scheme not only contains comparator noise, but also quantization noise of the ADC, and the statistical analysis process is realized on a chip at great cost, which is not beneficial to cost reduction. The simulation tool cannot cover all process deviation conditions in the actual chip manufacturing process, so that the noise performance is estimated incompletely. Factors such as electromagnetic interference and temperature change in the actual working environment are difficult to accurately simulate in simulation, and these factors may affect the noise performance of the comparator. The noise analysis of the ADC directly cannot account for the noise level of the comparator, and its calculation process is difficult to integrate on-chip. Therefore, the invention provides an on-chip automatic estimation method of the noise voltage of the comparator for improving the usability in engineering. This section is intended to provide a background or context for understanding the embodiments of the application and is not to be construed as an admission that the applicant is prior art to the present application that has been disclosed prior to the filing date of this application. Disclosure of Invention The application aims to provide a comparator noise estimation method of a successive approximation type analog-to-digital converter, which realizes on-chip automatic estimation of the noise voltage of a comparator, can estimate the actual noise of the comparator, and simultaneously avoids deviation between the simulated noise of the comparator and the actual situation. The application discloses a comparator noise estimation method of a successive approximation type analog-to-digital converter, which comprises a first capacitor array, a second capacitor array, a comparator and a logic control circuit, wherein a top plate of each capacitor in the first capacitor array is connected to a negative input end of the comparator and is connected to a common mode voltage through a sampling switch, a top plate of each capacitor in the second capacitor array is connected to a positive input end of the comparator and is connected to the common mode voltage through the sampling switch, an output end of the comparator is coupled to the logic control circuit, and