CN-121691956-B - Light-weight reading circuit for large-array SPAD real-time data compression

CN121691956BCN 121691956 BCN121691956 BCN 121691956BCN-121691956-B

Abstract

The invention relates to a light-weight readout circuit for large array SPAD real-time data compression, which belongs to the technical field of digital image processing and comprises a wavelet transformation unit, a Gaussian filter unit, a sliding window interception unit and a 4-way 8-bit bitwise lookup table serving as a reconfigurable calculation unit. The wavelet transformation unit converts the serial real-time data stream into a parallel data stream, and isolates the interference among pixels through zero padding operation to realize data compression. The Gaussian filter unit registers data through the line buffer and column buffer modules and provides parallel input for the calculation unit, and feature enhancement is efficiently completed in a separable convolution mode. And the sliding window intercepting unit performs sliding window summation on the filtered data, and extracts a peak value and an index thereof as final compressed output. The reconfigurable computing unit replaces the traditional multiplier by converting multiplication operation into lookup table lookup and pipeline accumulation operation, and provides efficient computation for wavelet transformation and Gaussian filtering.

Inventors

Bao Yaoqi
YAN ZHUANG
LI DONG
FENG LICHEN
MA RUI
ZHU ZHANGMING

Assignees

西安电子科技大学杭州研究院
西安电子科技大学

Dates

Publication Date: 20260512
Application Date: 20260211

Claims (8)

1. The light-weight reading circuit for large array SPAD real-time data compression is characterized by comprising a reconfigurable computing unit, a wavelet transformation unit, a Gaussian filter unit and a sliding window intercepting unit; the reconfigurable computing unit is a distributed arithmetic computing unit based on a lookup table and is configured to serve the wavelet transformation unit and the Gaussian filtering unit and is used for converting multiplication operation into lookup table lookup and pipeline accumulation operation; the wavelet transformation unit is used for receiving the serial real-time data stream output by the SPAD array, converting the serial real-time data stream into a parallel continuous data stream, and performing wavelet decomposition calculation to extract low-frequency approximation coefficients; The Gaussian filter unit is connected with the wavelet transformation unit and is used for carrying out Gaussian kernel convolution filter processing on the low-frequency approximation coefficients; The sliding window intercepting unit is connected to the Gaussian filtering unit and is used for carrying out sliding window summation on the filtered data stream, extracting peak characteristics and position indexes thereof and taking the peak characteristics and the position indexes as compressed output data; The distributed arithmetic computing unit is a multipath bitwise lookup table computing unit and is used for processing multipath parallel SPAD pixel data, wherein the bitwise lookup table computing unit comprises a lookup table, a pipeline adder and a plurality of bit computing units, wherein the number of the lookup table, the pipeline adder and the bit computing units correspond to the bit width of input data; The bit computing units are configured to respectively extract bits with the same weight from multiple paths of parallel input data, the bits are combined to form a lookup address to inquire the lookup table, coefficient part sums calculated by algorithm coefficients based on wavelet transformation and Gaussian filtering are stored in the lookup table in advance, and after the inquiry result is shifted according to the weights of the bits, the pipeline adder is used for accumulating to obtain a multiplication result.
2. The large array SPAD real time data compression oriented lightweight readout circuit according to claim 1, wherein said reconfigurable computing unit is caused to perform multiplication operations required in said wavelet decomposition computation and gaussian kernel convolution filtering processing, respectively, by configuring contents of said lookup table.
3. The light-weight readout circuit for large-array SPAD real-time data compression according to claim 1, wherein the wavelet transformation unit comprises a data rearrangement module, a parallel processing pipeline and an addition tree, wherein the data rearrangement module is used for rearranging serial data into parallel data streams, the parallel processing pipeline is composed of a plurality of cascaded reconfigurable computing units, and the addition tree is used for accumulating output results of the parallel processing pipeline to obtain the low-frequency approximation coefficients.
4. A lightweight readout circuit for large array SPAD real time data compression according to claim 3, wherein said data rearrangement module is further configured to perform zero padding operation between input data of adjacent pixels to isolate influence of adjacent pixels on said low frequency approximation coefficients.
5. The lightweight readout circuit for large array SPAD real-time data compression according to claim 1, wherein the gaussian filter unit comprises a line buffer module, a column buffer module, a line transform processing module and a column transform processing module, the line buffer module is used for buffering a plurality of lines of coefficient data and providing parallel line sliding window data for the line transform processing module, the column buffer module is used for buffering a plurality of columns of intermediate results after line transform and providing parallel line sliding window data for the column transform processing module, and the gaussian kernel convolution filter processing is realized in a separable convolution manner; The row transformation processing module and the column transformation processing module both take the reconfigurable computing unit as a computing component.
6. The large array SPAD real time data compression oriented lightweight readout circuit according to claim 5, wherein said line buffer module is comprised of a multi-stage register for registering and reorganizing said low frequency approximation coefficients into said parallel line sliding window data for one-dimensional convolution in a line direction; The column buffer module is composed of a multi-stage register and is used for registering the intermediate result after line transformation and recombining the intermediate result into the parallel column sliding window data so as to realize one-dimensional convolution in a column direction.
7. The light-weight readout circuit for large array SPAD real-time data compression according to claim 1, wherein the sliding window intercepting unit comprises a sliding window register chain, an adder tree, a comparator and an index register, wherein the sliding window register chain is used for caching continuous data, the adder tree is used for calculating an accumulated sum of data in a sliding window in parallel, the comparator is used for comparing a maximum value of the accumulated sum and taking the maximum value as the peak characteristic, and the index register is used for recording the position index corresponding to the peak characteristic.
8. The large array SPAD real time data compression oriented lightweight readout circuit according to claim 1, wherein said wavelet transform unit, said gaussian filter unit, said sliding window intercept unit, and said reconfigurable computing unit all employ pipeline architecture and are integrated in a programmable logic gate array.

Description

Light-weight reading circuit for large-array SPAD real-time data compression Technical Field The invention belongs to the technical field of digital image processing, and particularly relates to a light-weight reading circuit for large-array SPAD real-time data compression. Background In high resolution and high frame rate applications, the amount of data generated per second by a large-scale SPAD (Single-Photon Avalanche Diode) array is too large, and even exceeds the bandwidth of data buses such as USB (Universal Serial Bus ), PCIE (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed peripheral component interconnect) and the like by an order of magnitude, in order to solve the bottleneck, wavelet transformation is adopted in the prior art to compress histogram data, and gaussian filtering is assisted to remove noise and smooth. However, the conventional hardware-based implementation of wavelet transform and gaussian filtering has limitations in that the conventional wavelet transform (such as a multi-stage filter architecture) causes a large amount of computational redundancy due to its inherent downsampling mechanism and the serial structure thereof is difficult to parallelize efficiently, and at the same time, the conventional gaussian filtering relies on a two-dimensional convolution kernel with a huge computational amount, which consumes computational resources and increases processing delay, resulting in difficulty in meeting the requirement of real-time processing. Furthermore, under extreme conditions, such as very low signal-to-back ratio or at low photon flux levels, SPAD detectors are very susceptible to interference from ambient light noise, making it difficult to distinguish between the target signal and the background light signal, making it difficult to achieve accurate reconstruction, and excessive compression can also lead to significant increases in reconstruction errors. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a light-weight reading circuit for large-array SPAD real-time data compression. In the hardware level, aiming at the calculation redundancy of the traditional wavelet transformation, convolution operation is adopted to replace the calculation of redundancy in the traditional wavelet transformation, so that the calculation efficiency is improved. Aiming at the problem of huge calculation amount of the traditional Gaussian filter, the method is realized by adopting a mode of decoupling two one-dimensional vectors (namely, separable two-dimensional convolution), and the calculation and memory access expenses caused by the two-dimensional convolution kernel are reduced. In the processing level, after wavelet transformation is carried out on SPAD histogram data, gaussian filtering is firstly adopted to carry out smoothing processing on transformation coefficients so as to optimize signal characteristics, inhibit noise and optimize the effect after compression reconstruction, and then a signal interval is defined through a sliding window intercepting unit. The technical problems to be solved by the invention are realized by the following technical scheme: the invention provides a light-weight reading circuit for large-array SPAD real-time data compression, which comprises a reconfigurable computing unit, a wavelet transformation unit, a Gaussian filter unit and a sliding window intercepting unit, wherein the reconfigurable computing unit is used for converting data into a plurality of data; the reconfigurable computing unit is a distributed arithmetic computing unit based on a lookup table and is configured to serve the wavelet transformation unit and the Gaussian filtering unit and is used for converting multiplication operation into lookup table lookup and pipeline accumulation operation; the wavelet transformation unit is used for receiving the serial real-time data stream output by the SPAD array, converting the serial real-time data stream into a parallel continuous data stream, and performing wavelet decomposition calculation to extract low-frequency approximation coefficients; The Gaussian filter unit is connected with the wavelet transformation unit and is used for carrying out Gaussian kernel convolution filter processing on the low-frequency approximation coefficients; And the sliding window intercepting unit is connected with the Gaussian filtering unit and is used for carrying out sliding window summation on the filtered data stream, extracting peak characteristics and position indexes thereof and taking the peak characteristics and the position indexes as compressed output data. In one embodiment of the invention, the distributed arithmetic computing unit is a multi-path bitwise lookup table computing unit used for processing multi-path parallel SPAD pixel data, the bitwise lookup table computing unit comprises a lookup table, a pipeline adder and a plurality of bit computing units, the number of the lookup table, th