CN-121692646-B - Memory device and method of manufacturing the same

CN121692646BCN 121692646 BCN121692646 BCN 121692646BCN-121692646-B

Abstract

The present disclosure relates to the field of semiconductors, and provides a memory device and a method of fabricating the same, wherein the memory device includes a substrate; the memory cell structure comprises a plurality of isolation structures which are arranged on a substrate at intervals along a first direction, wherein the isolation structures comprise a main body part and a first widened part which is positioned on one side of the main body part, the main body part and the first widened part are arranged along a second direction, the width of the first widened part is larger than that of the main body part along the first direction, the memory cell structure is positioned between adjacent isolation structures, the memory cell structure comprises bit lines which extend along the vertical direction, and the bit lines are positioned between the adjacent first widened parts. The reliability of the memory device can be improved.

Inventors

LIU MINGYUAN
YUAN LIN
SUN ZHENG
LIANG TAO

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260210

Claims (12)

1.A memory device, comprising: A substrate; a plurality of isolation structures arranged on the substrate at intervals along a first direction, wherein the isolation structures comprise a main body part and a first widened part positioned at one side of the main body part, the main body part and the first widened part are arranged in a second direction, and the width of the first widened part is larger than that of the main body part along the first direction; and the memory cell structure is positioned between the adjacent isolation structures and comprises bit lines extending along the vertical direction, and the bit lines are positioned between the adjacent first widened parts.
2. The memory device of claim 1, wherein the body portion is of unitary construction with the first widened portion.
3. The memory device of claim 1, wherein a material of the body portion is different from a material of the first widened portion.
4. A memory device according to any one of claims 1 to 3, wherein the isolation structure further comprises a second widened portion on opposite sides of the body portion from the first widened portion, respectively, and the memory cell structure further comprises a capacitive structure between adjacent body portions and further between adjacent second widened portions.
5. The memory device of claim 4, wherein the first widened portion, the body portion, and the second widened portion are of unitary construction.
6. A memory device according to any one of claims 1 to 3, wherein the isolation structure further comprises: A first isolation portion located on a side of the main body portion away from the first widened portion, and having a width in the first direction that is less than or equal to a width of the main body portion; And the second isolation part is positioned on one side of the first isolation part away from the main body part, and the width of the second isolation part is smaller than that of the first isolation part along the first direction.
7. The memory device of claim 1, wherein the memory cell structure further comprises: A plurality of semiconductor parts sequentially arranged along the vertical direction, wherein the bit line is electrically contacted with one ends of the semiconductor parts, and the dimension of the part, which is clamped between the first widened parts, of the semiconductor parts along the first direction is gradually reduced in the direction facing the bit line; a plurality of word lines located on a part of the surface of the corresponding semiconductor portion and extending in the first direction.
8. A method of fabricating a memory device, comprising: Providing a substrate and a laminated structure on the substrate, wherein the laminated structure comprises sacrificial layers and semiconductor layers which are alternately arranged in the vertical direction; Forming a plurality of isolation structures which are arranged at intervals along a first direction on the substrate, wherein the isolation structures penetrate through the laminated structure and comprise a main body part and a first widened part positioned at one side of the main body part, the main body part and the first widened part are arranged along a second direction, and the width of the first widened part is larger than that of the main body part along the first direction; Removing the sacrificial layer; And forming a memory cell structure between adjacent isolation structures, wherein the semiconductor layer is partially removed in the step of forming the memory cell structure, and the rest of the semiconductor layer forms a semiconductor portion, wherein the memory cell structure comprises a bit line extending along the vertical direction, the bit line is positioned between adjacent first widened portions, and the bit line is electrically contacted with one end of the semiconductor portion.
9. The method of manufacturing a memory device according to claim 8, wherein the isolation structure further comprises a second widened portion, the second widened portion and the first widened portion are located on opposite sides of the main body portion, the second widened portion, the main body portion and the first widened portion are integrated, and the forming the bit line further comprises: Forming an insulating layer, wherein the insulating layer is positioned between adjacent semiconductor layers; removing part of the semiconductor layer to form a capacitor groove, wherein the capacitor groove is positioned at one side of the semiconductor part far away from the bit line; And forming a capacitor structure, wherein the capacitor structure fills the capacitor groove, is positioned between the adjacent main body parts and is also positioned between the adjacent second widened parts.
10. The method of claim 8, wherein forming the isolation structure comprises forming an initial isolation structure that extends through the stacked structure and includes a main body portion and an initial first widened portion on a side of the main body portion, the initial first widened portion having a width greater than a width of the main body portion; removing the initial first widening to form a first trench; after removing part of the sacrificial layer based on the first trench, filling the first trench to form a first widened portion, wherein the first widened portion and the main body portion form the isolation structure.
11. The method of claim 8, wherein forming the isolation structure comprises forming an initial isolation structure that extends through the stacked structure and includes a main body portion and initial first and second widened portions on opposite sides of the main body portion, the initial first and second widened portions having a width greater than a width of the main body portion; removing the initial first widening to form a first trench; removing a portion of the sacrificial layer based on the first trench, and then filling the first trench to form a first widened portion; removing the initial second widening to form a second trench; Forming an initial first isolation part and an initial second isolation part, wherein the initial first isolation part covers the inner wall of the second groove, and the initial second isolation part fills the second groove; And etching the initial first isolation part and the initial second isolation part to form a first isolation part and a second isolation part, wherein the width of the first isolation part is smaller than or equal to that of the main body part, and the width of the second isolation part is smaller than that of the first isolation part.
12. The method of fabricating a memory device according to claim 10 or 11, wherein the method of forming the memory cell structure comprises: After the first groove is formed, etching the sacrificial layer and part of the semiconductor layer along the first groove to expose the surface of the semiconductor layer; Forming a word line located on the exposed surface of the semiconductor layer and extending along the first direction; forming the bit line after forming the first widened portion; Etching the semiconductor layer to form a semiconductor portion; A capacitance structure is formed, and the capacitance structure is positioned on one side of the semiconductor part away from the bit line.

Description

Memory device and method of manufacturing the same Technical Field The present disclosure relates to the field of semiconductors, and more particularly, to a memory device and a method of fabricating the same. Background A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor device commonly used in electronic equipment such as a computer, and is composed of a plurality of memory cells, each of which generally includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor, and the voltage on the word line can control the transistor to be turned on and off, so that the data information stored in the capacitor can be read or written through the bit line. With the continuous miniaturization of memory structures such as DRAM, the structure of the semiconductor memory is spatially expanded upwards by using a three-dimensional (Three Dimensional, 3D) structure, which is greatly helpful for the development of memories such as dynamic random access memories. However, the risk of leakage between structures becomes more serious due to the increase in the integration level, and thus, it is required to reduce the generation of leakage, thereby improving the reliability of the semiconductor structure. Disclosure of Invention The present disclosure provides a memory device and a method of fabricating the same, which can at least reduce leakage of the memory device. The memory device comprises a substrate, a plurality of isolation structures arranged on the substrate at intervals along a first direction, the isolation structures comprise main body parts and first widened parts arranged on one side of the main body parts, the main body parts and the first widened parts are arranged in a second direction, the width of the first widened parts is larger than that of the main body parts along the first direction, the memory cell structures are located between adjacent isolation structures, the memory cell structures comprise bit lines extending along a vertical direction, and the bit lines are located between adjacent first widened parts. Optionally, the main body portion and the first widened portion are of unitary construction. Optionally, the material of the main body portion is different from the material of the first widened portion. Optionally, the isolation structure further comprises a second widened portion, the second widened portion and the first widened portion are respectively located at two opposite sides of the main body portion, the storage unit structure further comprises a capacitor structure, the capacitor structure is located between adjacent main body portions, and the capacitor structure is located between the adjacent second widened portions. Optionally, the first widened portion, the main body portion and the second widened portion are of unitary construction. Optionally, the isolation structure further comprises a first isolation part, wherein the first isolation part is positioned at one side of the main body part far away from the first widened part, the width of the first isolation part is smaller than or equal to that of the main body part along the first direction, and the second isolation part is positioned at one side of the first isolation part far away from the main body part, and the width of the second isolation part is smaller than that of the first isolation part along the first direction. Optionally, the memory cell structure further comprises a plurality of semiconductor parts sequentially arranged along the vertical direction, wherein the bit lines are electrically contacted with one ends of the plurality of semiconductor parts, the dimension of the part, sandwiched between the first widened parts, of the semiconductor parts along the first direction is gradually reduced in the direction towards the bit lines, and the plurality of word lines are positioned on part of the surfaces of the corresponding semiconductor parts and extend along the first direction. The memory device comprises a substrate, a laminated structure arranged on the substrate and comprising sacrificial layers and semiconductor layers which are alternately arranged in the vertical direction, a plurality of isolation structures which are arranged at intervals along the first direction and penetrate through the laminated structure and comprise main body parts and first widened parts which are arranged on one side of the main body parts, the main body parts and the first widened parts are arranged in the second direction, the width of the first widened parts is larger than that of the main body parts in the first direction, the sacrificial layers are removed, a memory cell structure is formed between the adjacent isolation structures, the semiconductor layers are partially removed in the step of forming the memory cell st