CN-121703629-B - Three-dimensional physical quantity decoupling monitoring system and method based on heterogeneous oscillator array

CN121703629BCN 121703629 BCN121703629 BCN 121703629BCN-121703629-B

Abstract

The application discloses a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array, and relates to the technical field of integrated circuits. The application constructs an orthogonal sensitivity matrix by designing a heterogeneous sensor array, comprising a logically dominant aging sensitive oscillator, a reference type oscillator and an interconnection line dominant oscillator and utilizing the characteristic that the interconnection line delay is insensitive to voltage and sensitive to temperature, adopts a double-mixing signal processing chain to generate beat frequency signals, combines a time division multiplexing hardware statistics accelerator to calculate the mean value and variance of the signals in real time, separates the temperature and the voltage fluctuation, suppresses common mode interference through a differential structure to extract aging signals, further realizes the decoupling monitoring of parameters in a chip, and can improve the monitoring accuracy.

Inventors

CHEN WANGYONG
CAI LINLIN

Assignees

中山大学

Dates

Publication Date: 20260505
Application Date: 20260211

Claims (8)

1. The three-dimensional physical quantity decoupling monitoring system based on the heterogeneous oscillator array is characterized by comprising a heterogeneous sensor array, a double-mixing signal processing chain, a prescaler, a selector, a time division multiplexing hardware statistic accelerator and a decoupling algorithm module; The heterogeneous sensor array comprises a logic dominant oscillator and an interconnection line dominant oscillator, wherein the logic dominant oscillator comprises an aging sensitive oscillator and a reference oscillator; the double-mixing signal processing chain comprises a mixer A and a mixer B; the aging sensitive oscillator is connected to the first end of the mixer A, and the base reference oscillator is connected to the second end of the mixer A; a second end of the prescaler is connected to a first end of the mixer B, and the interconnect-dominant oscillator is connected to the second end of the mixer B; The third terminal of the mixer A is connected to the first terminal of the selector, and the third terminal of the mixer B is connected to the second terminal of the selector; A third end of the selector is connected to a first end of the time division multiplexing hardware statistics accelerator, and a second end of the time division multiplexing hardware statistics accelerator is connected to the decoupling algorithm module; The time division multiplexing hardware statistics accelerator comprises a period measurement unit, an accumulator, a square accumulator, a DSP multiplication unit and a control state machine; The input end of the period measuring unit is used for receiving the beat frequency signal output by the selector, the first output end of the period measuring unit is connected to the input end of the accumulator, the second output end of the period measuring unit is connected to the input end of the DSP multiplication unit, the third output end of the period measuring unit is connected to the first end of the control state machine, and the fourth output end of the period measuring unit is used for outputting a sampling count value; The output end of the DSP multiplication unit is connected to the input end of the square accumulator; A second end of the control state machine is interconnected with the accumulator, and a third end of the control state machine is interconnected with the square accumulator; The output end of the accumulator is used for outputting a summation item; The output end of the square accumulator is used for outputting a square summation term; The period measuring unit is used for counting the clock number between two rising edges of the beat frequency signal to obtain a count value x i of a sampling period; the accumulator is used for performing one accumulation, acc 1 = Acc 1 +x i ; The DSP multiplication unit is used for calculating x i 2 ; the square accumulator is used for performing secondary accumulation, acc 2 = Acc 2 +x i 2 ; the decoupling algorithm module is configured to perform: Acc 1 and Acc 2 were read; Calculating mu=Acc 1 /N, and reversely solving the current temperature T of the chip to be tested by utilizing the temperature coefficient K WireT of the interconnection line leading type oscillator, wherein N is the total number of samples; Calculating sigma 2 = (Acc 2 / N) - μ 2 , and reversely solving the voltage ripple amplitude by utilizing the voltage sensitivity S RefV of the reference type oscillator 。
2. The three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array according to claim 1, wherein the interconnect line dominant oscillator is driven by logic gates and comprises metal interconnect lines reaching a set length threshold; The path delay of the interconnect-dominant oscillator is more than 90% realized by the delay of the resistance and capacitance of the metal lines.
3. The three-dimensional physical quantity decoupling monitor system based on a heterogeneous oscillator array according to claim 2, wherein in the FPGA, by making signals wire-wound or wire-routed across a long column between a plurality of logic array blocks, a path delay of 90% or more of the interconnect line dominant oscillator is realized by a delay of resistance and capacitance of a metal line.
4. The three-dimensional physical quantity decoupling monitoring system based on the heterogeneous oscillator array according to claim 1, wherein the aging sensitive oscillator is formed by connecting CMOS logic gates end to end, wherein the CMOS logic gates adopt lookup tables LUTs or inverters in FPGA; the working mode of the aging sensitive oscillator is normally open.
5. The three-dimensional physical quantity decoupling monitoring system based on the heterogeneous oscillator array according to claim 1, wherein the reference oscillator is formed by connecting CMOS logic gates end to end, and the CMOS logic gates adopt lookup tables LUTs or inverters in FPGA; The working mode of the reference oscillator is gating.
6. A three-dimensional physical quantity decoupling monitoring method based on a heterogeneous oscillator array, wherein the method is applied to the three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array as claimed in claim 1, and the method comprises the following steps: By utilizing the physical characteristic difference of the logic leading oscillator and the interconnection leading oscillator, the following equation set is established, so that the temperature T to be measured of the chip to be measured is decoupled and separated from the voltage V to be measured: ; Wherein y Logic is the frequency normalization variable quantity of the logic leading oscillator, y Wire is the frequency normalization variable quantity of the interconnection line leading oscillator, S L,T ,S L,V is the sensitivity coefficient of the logic leading oscillator to temperature and voltage respectively, S W,T ,S W,V is the sensitivity coefficient of the interconnection line leading oscillator to temperature and voltage respectively; Calculating the aging parameters to be measured of the chip to be measured by using the differential structure of the aging sensitive oscillator and the reference oscillator, wherein the method specifically comprises the following steps: ; Wherein, the A represents the aging parameter to be measured, Representing an initial beat frequency value measured during a calibration phase for compensating for a fixed offset caused by process variations; Representing the difference frequency signal processed by the mixer a, derived from the subtraction of the frequency of the baseline reference oscillator and the frequency of the aging sensitive oscillator, Representing the output frequency of the reference oscillator under V, T conditions, Representing the output frequency of the aging sensitive oscillator under the conditions of V, T and A; Calculating the average value of sampling period count values of the heterogeneous sensor array as the temperature to be measured of the chip to be measured; And calculating the variance of the sampling period count value of the heterogeneous sensor array as the voltage to be measured of the chip to be measured.
7. The three-dimensional physical quantity decoupling monitoring method based on the heterogeneous oscillator array according to claim 6, wherein the calculating the average value of the sampling period count values of the heterogeneous sensor array as the temperature to be measured of the chip to be measured comprises the following steps: calculating the average mu as the temperature to be measured of the chip to be measured through the following expression; ; Wherein x i is the count value of the ith sampling period, and N is the total number of samples; the calculating the variance of the sampling period count value of the heterogeneous sensor array as the voltage to be measured of the chip to be measured comprises the following steps: calculating the variance sigma 2 as a voltage to be measured of the chip to be measured by the following expression; ; Wherein E x 2 represents the average value of the square of the count value of the sampling period, and E x represents the average value of the count value of the sampling period.
8. The method for monitoring three-dimensional physical quantity decoupling based on a heterogeneous oscillator array according to claim 6, wherein the method further comprises the step of in-situ self-calibration, in particular comprising the steps of: And carrying out in-situ process deviation calibration, temperature coefficient calibration and voltage sensitivity calibration on the three-dimensional physical quantity decoupling monitoring system.

Description

Three-dimensional physical quantity decoupling monitoring system and method based on heterogeneous oscillator array Technical Field The application relates to the technical field of integrated circuits, in particular to a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array. Background Currently, the industry and academia mainly adopt three technical schemes of a scheme I, a scheme II and a scheme III, wherein the scheme I is based On an odometer (Odometer) technology of a Ring Oscillator (RO), the scheme II is a key path monitoring (CRITICAL PATH Monitor, CPM) or a canary trigger (CANARY FLIP-flop), and the scheme III is an On-chip analog-digital converter (On-Chip Analog Sensor/ADC). Although the above technologies have been applied, they face the defects of inaccurate measurement, indiscriminate separation and incapacitation of three cores under the deep submicron process, and cannot meet the requirement of fine management of the health state of the chip. Disclosure of Invention The embodiment of the application mainly aims to provide a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array so as to improve the monitoring accuracy of physical parameters inside a chip. In order to achieve the above purpose, one aspect of the embodiments of the present application provides a three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array, the system includes a heterogeneous sensor array, a double mixing signal processing chain, a prescaler, a selector, a time division multiplexing hardware statistics accelerator and a decoupling algorithm module; The heterogeneous sensor array comprises a logic dominant oscillator and an interconnection line dominant oscillator, wherein the logic dominant oscillator comprises an aging sensitive oscillator and a reference oscillator; the double-mixing signal processing chain comprises a mixer A and a mixer B; the aging sensitive oscillator is connected to the first end of the mixer A, and the base reference oscillator is connected to the second end of the mixer A; a second end of the prescaler is connected to a first end of the mixer B, and the interconnect-dominant oscillator is connected to the second end of the mixer B; The third terminal of the mixer A is connected to the first terminal of the selector, and the third terminal of the mixer B is connected to the second terminal of the selector; The third terminal of the selector is connected to a first terminal of the time division multiplexing hardware statistics accelerator, and a second terminal of the time division multiplexing hardware statistics accelerator is connected to the decoupling algorithm module. In some embodiments, the time division multiplexing hardware statistics accelerator comprises a period measurement unit, an accumulator, a square accumulator, a DSP multiplication unit, and a control state machine; The input end of the period measuring unit is used for receiving the beat frequency signal output by the selector, the first output end of the period measuring unit is connected to the input end of the accumulator, the second output end of the period measuring unit is connected to the input end of the DSP multiplication unit, the third output end of the period measuring unit is connected to the first end of the control state machine, and the fourth output end of the period measuring unit is used for outputting a sampling count value; The output end of the DSP multiplication unit is connected to the input end of the square accumulator; A second end of the control state machine is interconnected with the accumulator, and a third end of the control state machine is interconnected with the square accumulator; The output end of the accumulator is used for outputting a summation item; The output end of the square accumulator is used for outputting a square summation term. In some embodiments, the period measurement unit is configured to count the number of clocks between two rising edges of the beat signal, and obtain a count value x i of a sampling period; the accumulator is used for performing one accumulation, acc 1= Acc1+xi; The DSP multiplication unit is used for calculating x i2; the square accumulator is used for performing secondary accumulation, acc 2= Acc2+xi2; the decoupling algorithm module is configured to perform: Acc 1 and Acc 2 were read; Calculating mu=Acc 1/N, and reversely solving the current temperature T of the chip to be tested by utilizing the temperature coefficient K WireT of the interconnection line leading type oscillator, wherein N is the total number of samples; Calculating sigma 2= (Acc2/ N) - μ2, and reversely solving the voltage ripple amplitude by utilizing the voltage sensitivity S RefV of the reference type oscillator 。 In some embodiments, the interconnect line dominant oscillator is driven by a logic gate