CN-121724086-B - Square resistance prediction model training method and square resistance prediction method

CN121724086BCN 121724086 BCN121724086 BCN 121724086BCN-121724086-B

Abstract

The invention discloses a square resistance prediction model training method and a square resistance prediction method, belonging to the technical field of semiconductors, wherein the method comprises the steps of obtaining a training set; according to the design rule of the optimization process, determining a plurality of relative differences of a plurality of key parameters of each sample in the optimization process and the training set, wherein the optimization process is optimized on the basis of the source process, obtaining a square resistance prediction model, constructing the square resistance prediction model based on the physical relationship between the square resistance and the plurality of key parameters, and training the square resistance prediction model by adopting the plurality of samples in the training set and the plurality of relative differences of each sample. The method can realize high-precision square resistance prediction.

Inventors

XU KE
CHEN JIAN
QIU RUMENG
QIN XUWEI
HUANG YIQUAN
Liu Zheru

Assignees

合肥晶合集成电路股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260211

Claims (10)

1. The square resistance prediction model training method is characterized by comprising the following steps of: obtaining a training set, wherein the training set comprises a plurality of samples, each sample comprises a square resistance of a kth transistor in a source process, a plurality of key parameters related to the square resistance, and the square resistance of the kth transistor in an optimization process, and the key parameters comprise a metal wire line width, a metal wire thickness and a metal material resistivity; Determining a plurality of relative differences of a plurality of key parameters of each sample in the optimization process and the training set according to design rules of the optimization process, wherein the optimization process is optimized on the basis of the source process; obtaining a square resistance prediction model, wherein the square resistance prediction model is constructed based on physical relations between square resistance and a plurality of key parameters; And training the square resistance prediction model by adopting a plurality of samples in a training set and a plurality of relative differences of each sample, and optimizing parameters of the square resistance prediction model by adopting a back propagation gradient method in the process of training the square resistance prediction model.
2. The method according to claim 1, wherein in the physical relationship between the square resistance and the plurality of key parameters, the square resistance is inversely proportional to the line width of the metal line and the thickness of the metal line, and the square resistance is directly proportional to the resistivity of the metal material; the square resistance prediction model comprises a neural network sub-model and a physical formula layer which are connected in sequence, wherein the neural network sub-model comprises an input layer, a first hiding layer, a second hiding layer and an output layer which are connected in sequence; the physical formula layer of the square resistance prediction model adopts the following formula to express: Wherein, the For the square resistance of the ith sample of the kth transistor in the source process, The block resistance of the ith sample of the kth transistor predicted by the block resistance prediction model in the optimization process, 、、 The physical relation coefficient in the square resistance prediction model is predicted by adopting the neural network submodel, the input of the neural network submodel is the plurality of relative differences, the output of the neural network submodel is the physical relation coefficient, For the relative difference between the line widths of the metal lines in the optimization process and the source process for the ith sample of the kth transistor, For the relative difference between the metal line thickness in the optimization process and the source process for the ith sample of the kth transistor, The relative difference between the resistivity of the metallic material in the optimization process and the source process is the ith sample of the kth transistor.
3. The method of claim 2, wherein the relative difference between the line widths of the metal lines in the optimization process and the source process for the ith sample of the kth transistor is calculated using the formula: Wherein, the For the metal line width indicated by the design rule of the optimization process for the kth transistor, A metal line width in the source process for an ith sample of the kth transistor; The relative difference between the thickness of the metal line in the optimization process and the source process for the ith sample of the kth transistor is calculated using the following formula: Wherein, the For the thickness of the metal line indicated by the design rule of the optimization process for the kth transistor, A metal line thickness in the source process for an ith sample of the kth transistor; the relative difference between the resistivity of the metal material in the optimization process and the source process for the ith sample of the kth transistor is calculated using the following formula: Wherein, the For the metal material resistivity indicated by the design rule of the optimization process for the kth transistor, The resistivity of the metallic material in the source process for the ith sample of the kth transistor.
4. A sheet resistance prediction model training method according to any one of claims 1 to 3, wherein in training the sheet resistance prediction model, a loss function is expressed by the following formula: Wherein, the Representing the predicted physical relationship coefficients of the neural network sub-model in the square resistance prediction model as a loss function 、、 Is added to the system, the loss of (a) is, The square resistance in the optimization process predicted by the square resistance prediction model on the ith sample corresponding to the kth transistor, The label of the ith sample corresponding to the kth transistor is the sample in the training set, i is a positive integer, and the value range of i is 1 to , And the total number of samples corresponding to the kth transistor in the training set is obtained.
5. A block resistance prediction method, characterized in that the block resistance prediction method comprises: Obtaining a plurality of key parameters of a target transistor, wherein the target transistor is a transistor actually produced in an optimization process, the target transistor belongs to a kth transistor, and the key parameters comprise a metal line width, a metal line thickness and a metal material resistivity; Obtaining a reference sample of a source process of a kth transistor, and calculating a plurality of relative differences of a plurality of key parameters of the target transistor and the reference sample; Inputting a plurality of relative differences of a plurality of key parameters of the target transistor and the reference sample of the source process of the kth transistor into a square resistance prediction model to obtain the square resistance of the target transistor in an optimization process; wherein the sheet resistance prediction model is obtained by the sheet resistance prediction model training method according to any one of claims 1 to 4.
6. A sheet resistance prediction model training device, characterized in that the sheet resistance prediction model training device comprises: A first obtaining module, configured to obtain a training set, where the training set includes a plurality of samples, each sample includes a square resistance of a kth transistor in a source process, a plurality of key parameters associated with the square resistance, and a square resistance of the kth transistor in an optimization process, where the plurality of key parameters include a metal line width, a metal line thickness, and a metal material resistivity; The relative difference determining module is used for determining a plurality of relative differences of a plurality of key parameters of each sample in the optimizing process and the training set according to the design rule of the optimizing process, and the optimizing process is optimized on the basis of the source process; The second acquisition module is used for acquiring a square resistance prediction model, and the square resistance prediction model is constructed based on the physical relationship between the square resistance and a plurality of key parameters; and the training module is used for training the square resistance prediction model by adopting a plurality of samples in a training set and a plurality of relative differences of each sample, and optimizing parameters of the square resistance prediction model by adopting a back propagation gradient method in the process of training the square resistance prediction model.
7. A square resistance prediction device is characterized in that, the square resistance prediction device includes: The first acquisition module is used for acquiring a plurality of key parameters of a target transistor, wherein the target transistor is a transistor actually produced in an optimization process, the target transistor belongs to a kth transistor, and the key parameters comprise a metal wire width, a metal wire thickness and a metal material resistivity; the second acquisition module is used for acquiring a reference sample of a source process of a kth transistor and calculating a plurality of relative differences of a plurality of key parameters of the target transistor and the reference sample; the square resistance prediction module is used for inputting a plurality of relative differences of a plurality of key parameters of the target transistor and the reference sample of the source process of the kth transistor into a square resistance prediction model to obtain the square resistance of the target transistor in an optimization process; wherein the sheet resistance prediction model is obtained by the sheet resistance prediction model training method according to any one of claims 1 to 4.
8. A computer device comprising a memory and a processor, wherein the memory stores at least one computer program that is loaded and executed by the processor to implement the sheet resistance prediction model training method of any one of claims 1 to 4 or the sheet resistance prediction method of claim 5.
9. A computer readable storage medium having stored therein at least one computer program loaded and executed by a processor to implement the sheet resistance prediction model training method of any one of claims 1 to 4 or the sheet resistance prediction method of claim 5.
10. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the sheet resistance prediction model training method of any one of claims 1 to 4 or the sheet resistance prediction method of claim 5.

Description

Square resistance prediction model training method and square resistance prediction method Technical Field The invention relates to the technical field of semiconductors, in particular to a square resistance prediction model training method and a square resistance prediction method. Background In 40 nm and more advanced semiconductor nodes, accurate prediction of sheet resistance (Rs) of metal layers in BeoL (Back End of Line) is critical to device performance, yield and reliability. The sheet resistance in advanced semiconductor process is strictly controlled to be 0.5-0.8(Or) The allowable fluctuation is less than 5%, but the thickness of the medium is uneven due to the variation of the CMP process (such as) And etching load, etc., the actual deviation of the square resistance is often 8-10%, and the electrical index of the semiconductor is seriously affected. Under the current manufacturing environment, the silicon wafer measurement data has the characteristics of multiple dimensions and high capacity (TB/batch), and the traditional method relying on manual experience is difficult to realize efficient and accurate square resistance prediction. This problem is particularly acute in new product development. The lack of accurate sheet resistance prediction results in an extended development cycle of the semiconductor, requiring 6-12 weeks for a single BEoL process iteration, and engineering streamer costs on the order of millions of dollars. To approach the optimal process window, a large number of parameter combinations (e.g., anneal temperature, deposition rate, CMP pressure, etc.) need to be verified, further increasing time and economic investment. The high-cost and long-period trial-and-error mode obviously slows down the technology maturation and the product marketing, and restricts the research and development of return on investment and commercialization process. Disclosure of Invention The invention provides a square resistance prediction model training method and a square resistance prediction method, which can realize high-precision square resistance prediction. The technical scheme at least comprises the following scheme: A method for training a square resistance prediction model includes the steps of obtaining a training set, wherein the training set comprises a plurality of samples, each sample comprises square resistance of a kth transistor in a source process, a plurality of key parameters related to the square resistance, and square resistance of the kth transistor in an optimization process, the key parameters comprise wire width, wire thickness and metal material resistivity, determining a plurality of relative differences of the key parameters of each sample in the optimization process and the training set according to design rules of the optimization process, the optimization process is optimized on the basis of the source process, obtaining a square resistance prediction model, the square resistance prediction model is constructed on the basis of physical relations between the square resistance and the key parameters, training the square resistance prediction model by adopting the samples in the training set and the relative differences of each sample, and optimizing parameters of the square resistance prediction model by adopting a reverse propagation gradient method in the process of training the square resistance prediction model. Optionally, in the physical relation between the square resistance and a plurality of key parameters, the square resistance is inversely proportional to the line width and the thickness of the metal line, and the square resistance is directly proportional to the resistivity of the metal material, and the square resistance prediction model is expressed by adopting the following formula: Wherein, the For the square resistance of the ith sample of the kth transistor in the source process,The block resistance of the ith sample of the kth transistor predicted by the block resistance prediction model in the optimization process,、、A neural network sub-model is adopted for predicting the physical relation coefficient in the square resistance prediction model, the neural network sub-model is one sub-model in the square resistance prediction model, the input of the neural network sub-model is the plurality of relative differences, the output of the neural network sub-model is the physical relation coefficient,For the relative difference between the line widths of the metal lines in the optimization process and the source process for the ith sample of the kth transistor,For the relative difference between the metal line thickness in the optimization process and the source process for the ith sample of the kth transistor,The relative difference between the resistivity of the metallic material in the optimization process and the source process is the ith sample of the kth transistor. Optionally, the relative difference between the line widths of the metal lines in the