CN-121747680-B - Decoding logic deducing method, invalid storage grain positioning method and related equipment

CN121747680BCN 121747680 BCN121747680 BCN 121747680BCN-121747680-B

Abstract

The embodiment of the application discloses a decoding logic deducing method, a failure storage grain positioning method and related equipment, which comprise the steps of collecting all first error physical addresses generated by testing the same failure storage grain in a first physical slot to form a first error physical address set, collecting all second error physical addresses generated by testing the same failure storage grain in a second physical slot to form a second error physical address set, searching the first error physical address set and the second error physical address set to find k address bits, wherein the binary logic values of the k address bits or logic combinations thereof in all the first error physical addresses are constant to be the same value, the binary logic values of the k address bits or logic combinations thereof in all the second error physical addresses are constant to be the inverse value of the same value, and generating a Boolean function of the k address bits or logic combinations thereof as decoding logic. The application can automatically restore the hidden physical address decoding logic and realize the automatic, accurate and efficient positioning of the physical position of the invalid storage particles.

Inventors

SUN CHENGSI
HE HAN
WANG CAN
Da Longke

Assignees

深圳佰维存储科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260225

Claims (12)

1. A method of deriving decoding logic for use in error physical address decoding of failed memory grain in a memory module having a plurality of memory grains, the method comprising: Collecting all first error physical addresses generated when the same invalid storage particle is tested in a first physical slot to form a first error physical address set; Collecting all second error physical addresses generated when the same invalid storage particle is tested in the second physical slot to form a second error physical address set; Searching the first error physical address set and the second error physical address set to find k address bits, wherein the k address bits or logic combinations thereof are constant in the binary logic values of all the first error physical addresses to be the same value, and the binary logic values of all the second error physical addresses are constant in the inverse value of the same value; generating a boolean function of the k address bits or a logical combination thereof as decoding logic for mapping the erroneous physical address of the failed memory granule to a physical slot identification; Wherein k is a natural number, and k is 1-1 and the number of bits of the address bits.
2. The method of claim 1, wherein searching the first set of erroneous physical addresses and the second set of erroneous physical addresses for k address bits comprises: Let k=1; Searching the first error physical address set and the second error physical address set, and finding 1 address bit, wherein the binary logic values of the address bits in all the first error physical addresses are constant to be the same value, and the binary logic values in all the second error physical addresses are constant to be the inverse value of the same value; If the 1 address bit is not found, the following searching steps are iteratively executed until the k address bits are found or the k value exceeds a preset limit value: Let k value add 1; And continuing to search the first error physical address set and the second error physical address set to find k address bits, wherein the logical combination of the k address bits is constant at the same value in the binary logic values of all the first error physical addresses, and constant at the inverse value of the same value in the binary logic values of all the second error physical addresses.
3. The decode logic derivation method of claim 2, further comprising, after said finding k address bits: and after replacing the same invalid storage particle with another invalid storage particle, repeating the searching steps until k address bits are found, and if the same k address bits are found, verifying that the searching result is correct.
4. The decoding logic derivation method of claim 3, wherein if the k address bits are found that are not identical, validating the search result error, and performing the steps of: and after replacing the other invalid storage particle again, starting the k value from the last search result to be added with 1, and repeating the searching steps until k address bits are found.
5. The method of claim 4, wherein in the generating the boolean function of the k address bits or the logical combination thereof: the k address bits are determined to be the first found k address bits, or The k address bits are determined as a result of the least number of address bits and the greatest bit index among the plurality of found k address bits.
6. The method of deriving decoding logic according to any one of claims 2-5, wherein the logical combination comprises at least one of AND, OR, NOT, XOR.
7. The method of claim 6, wherein the logical combination is the value of the 1 address bits or a logical not thereof when k=1, or comprises an exclusive OR operation when k≥2.
8. The decoding logic derivation method of any one of claims 1-5, wherein the boolean function is set to a disjunctive or conjunctive normal form.
9. The method for positioning the invalid storage particles is applied to positioning the invalid storage particles in a storage module with a plurality of storage particles, and is characterized by comprising the following steps: In response to detecting the failure of the storage particles, converting the error physical address of the failed storage particles into a corresponding physical slot identifier according to a preset decoding logic; Mapping the physical slot identification to a physical location identification of the failed storage particle; Wherein the preset decoding logic is set as a boolean function generated according to the decoding logic derivation method of any one of claims 1-8.
10. The method for locating a failed storage grain according to claim 9, wherein the mapping the physical slot identifier to the physical location identifier of the failed storage grain specifically comprises: And determining the corresponding physical position identification of the invalid storage particles on the storage module based on the column address bits in the error physical address and the bit width configuration of the storage particles.
11. A test apparatus comprising a processor and a memory coupled to the processor, the memory for storing computer program code, the computer program code comprising computer instructions which, when read from the memory by the processor, cause the processor to perform the steps in the method of any of claims 1-10.
12. A computer program product, characterized in that the computer program product comprises computer program code for causing a computer to carry out the steps of the method as claimed in any one of claims 1-10 when said computer program code is run on a computer.

Description

Decoding logic deducing method, invalid storage grain positioning method and related equipment Technical Field Embodiments of the present application relate to the field of memory testing, and in particular, to a method for deriving an error physical address decoding logic of a memory chip, a method for locating failed memory particles, a test apparatus, and a computer program product. Background With the continuous increase of the memory capacity and performance requirements of computing systems, the topology structure of the storage system is increasingly complex, and multi-channel, multi-Socket, and high-density memory modules have become standard of servers, workstations, and high-performance computing platforms. In such systems, a Central Processing Unit (CPU) maps the system physical address space to specific memory particles distributed across a plurality of physical slots through its Integrated Memory Controller (IMC). This mapping process typically involves complex address decoding logic, possibly including address bit Interleaving (Interleaving), chip select (CHIP SELECT) combinations, etc., to achieve bandwidth optimization and load balancing. Memory modules typically include a plurality of memory particles distributed among different physical slots. When the system detects that a certain storage grain fails, an error physical address is reported, but the address is usually a logical address and does not directly correspond to a physical slot or a storage grain position. Since the address mapping logic of the different platforms (CPU, motherboard, BIOS combination) may be quite different and is not typically disclosed to the user. Thus, at the system level, it is not directly known from the wrong physical address list of the failed storage grain which storage grain is problematic. The existing positioning method relies on manual analysis, and is low in efficiency and easy to make mistakes. Disclosure of Invention The embodiment of the application provides a decoding logic deducing method, a failure storage grain positioning method, test equipment and a computer program product, which are used for automatically restoring hidden physical address decoding logic and realizing automatic, accurate and efficient positioning of the physical position of the failure storage grain. In a first aspect, an embodiment of the present application provides a method for deriving decoding logic, which is applied to error physical address decoding of a failed storage granule in a storage module having a plurality of storage granules, where the method includes: Collecting all first error physical addresses generated when the same invalid storage particle is tested in a first physical slot to form a first error physical address set; Collecting all second error physical addresses generated when the same invalid storage particle is tested in the second physical slot to form a second error physical address set; Searching the first error physical address set and the second error physical address set to find k address bits, wherein the k address bits or logic combinations thereof are constant in the binary logic values of all the first error physical addresses to be the same value, and the binary logic values of all the second error physical addresses are constant in the inverse value of the same value; generating a boolean function of the k address bits or a logical combination thereof as decoding logic for mapping the erroneous physical address of the failed memory granule to a physical slot identification; Wherein k is a natural number, and k is 1-1 and the number of bits of the address bits. By implementing the embodiment of the application, the address bit combination with stable logic difference is automatically searched in the error address set generated when the same invalid storage particle is tested in different physical slots, the decoding logic is deduced, the automatic mapping from the system error address to the physical slot can be realized without manual intervention or presetting a mapping table, and the positioning efficiency and accuracy are obviously improved. In at least one possible implementation manner, the searching the first set of wrong physical addresses and the second set of wrong physical addresses to find k address bits specifically includes: Let k=1; Searching the first error physical address set and the second error physical address set, and finding 1 address bit, wherein the binary logic values of the address bits in all the first error physical addresses are constant to be the same value, and the binary logic values in all the second error physical addresses are constant to be the inverse value of the same value; If the 1 address bit is not found, the following searching steps are iteratively executed until the k address bits are found or the k value exceeds a preset limit value: Let k value add 1; And continuing to search the first error physical address set and the second error physical