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CN-121752034-B - Semiconductor structure and preparation method thereof

CN121752034BCN 121752034 BCN121752034 BCN 121752034BCN-121752034-B

Abstract

The invention provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a plurality of semiconductor devices which are arranged in parallel, each semiconductor device comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, the metal interconnection structure is arranged in a dielectric layer, a second well region arranged in the substrate between the first well regions of adjacent semiconductor devices, an insulating layer arranged on the dielectric layer between the adjacent semiconductor devices and extending to two sides to part of the metal interconnection structure, a passivation layer arranged on the insulating layer, a first groove arranged on the surface of the metal interconnection structure and exposing part of the metal interconnection structure, and a second groove arranged on the metal interconnection structure in a surrounding manner of the first groove and exposing part of the insulating layer. The semiconductor structure and the preparation method thereof provided by the invention can reduce the influence of ambient humidity on the measurement of the leakage current.

Inventors

  • ZHU JUNLONG
  • Liu Zheru

Assignees

  • 合肥晶合集成电路股份有限公司

Dates

Publication Date
20260505
Application Date
20260302

Claims (10)

  1. 1. A semiconductor device is provided, which is a semiconductor device, characterized in that it comprises at least: A plurality of semiconductor devices arranged in parallel, each semiconductor device at least comprising at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, wherein the metal interconnection structure is arranged in a dielectric layer; a second well region disposed within the substrate between the first well regions of adjacent semiconductor devices; The insulating layer is arranged on the dielectric layer between the adjacent semiconductor devices and extends to two sides to part of the metal interconnection structure; A passivation layer disposed on the insulating layer; A first groove arranged on the surface of the metal interconnection structure and exposing part of the metal interconnection structure, and And a second groove surrounding the first groove and arranged on the metal interconnection structure, and exposing part of the insulating layer.
  2. 2. The semiconductor structure of claim 1, wherein a ratio between a loop width of the second recess and a depth of inward depression of the second recess is (5-50): 1.
  3. 3. The semiconductor structure of claim 1, wherein a ratio between a spacing between the first recess and the second recess and a depth of inward depression of the second recess is greater than 1.
  4. 4. The semiconductor structure of claim 1, wherein the passivation layer has a thickness greater than 100nm and the insulating layer has a thickness less than the thickness of the passivation layer.
  5. 5. A method for fabricating a semiconductor structure, comprising at least the steps of: Providing a plurality of semiconductor devices arranged in parallel, wherein each semiconductor device at least comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, and the metal interconnection structure is arranged in a dielectric layer; Forming a second well region in the substrate between the first well regions of adjacent semiconductor devices; Forming an insulating layer on the dielectric layer between the adjacent semiconductor devices, wherein the insulating layer extends to two sides to part of the metal interconnection structure; forming a passivation layer on the insulating layer; Forming a first groove on the surface of the metal interconnection structure, wherein the first groove exposes part of the metal interconnection structure, and A second recess is formed on the metal interconnect structure surrounding the first recess, and the second recess exposes a portion of the insulating layer.
  6. 6. The method of manufacturing as claimed in claim 5, wherein when forming the first and second recesses, a first photoresist layer is first formed on the passivation layer, a first opening exposing a portion of the passivation layer on the metal interconnect structure and a second opening disposed around the first opening exposing a portion of the passivation layer on the metal interconnect structure, and a width of the first opening is greater than a ring width of the second opening.
  7. 7. The method of manufacturing according to claim 6, wherein after the first opening and the second opening are formed, the passivation layer exposed by the first opening and the second opening is etched with the first photoresist layer as a mask and the insulating layer under the first opening as an etching stop layer, forming a first recess and a second recess, the second recess being recessed inward from the passivation layer to a surface of the insulating layer, the first recess being disposed around the second recess and recessed inward from the passivation layer.
  8. 8. The method of manufacturing according to claim 7, wherein after the first recess and the second recess are formed, the insulating layer exposed in the second recess is selectively etched away to form the first groove, and then the passivation layer on the bottom of the first recess is selectively removed to form the second groove.
  9. 9. The method of manufacturing a semiconductor device according to claim 5, wherein when forming the first recess and the second recess, a second photoresist layer is first formed on the passivation layer, a third opening is formed in the second photoresist layer, the third opening exposes a portion of the passivation layer on the metal interconnection structure, then the second photoresist layer is used as a mask, the metal interconnection structure is used as a stop layer, and the passivation layer and the insulating layer exposed by the third opening are etched and removed to form the first recess.
  10. 10. The method of manufacturing as claimed in claim 9, wherein after the first recess is formed, a third photoresist layer is formed on the passivation layer and in the first recess, a fourth opening is formed in the third photoresist layer, the fourth opening is disposed on the passivation layer around the first recess, and then the passivation layer exposed by the fourth opening is etched with the third photoresist layer as a mask and the insulating layer as a stop layer, thereby forming the second recess.

Description

Semiconductor structure and preparation method thereof Technical Field The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background In a semiconductor device, when junction leakage current between an N well and a P well is measured, a microscopic water film is easily formed on a passivation layer between two electrodes under test under the influence of ambient humidity, the microscopic water film forms an additional conductive path, and additional leakage current is introduced, so that an actual measured value contains two parts of the junction leakage current and the water film leakage current, and accurate measurement of the junction leakage current is disturbed. Disclosure of Invention The invention aims to provide a semiconductor structure and a preparation method thereof, which can reduce the influence of ambient humidity on the leakage current measurement, thereby improving the accuracy of electrical measurement. In order to solve the technical problems, the invention is realized by the following technical scheme: the invention provides a semiconductor structure, which at least comprises: A plurality of semiconductor devices arranged in parallel, each semiconductor device at least comprising at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, wherein the metal interconnection structure is arranged in a dielectric layer; a second well region disposed within the substrate between the first well regions of adjacent semiconductor devices; The insulating layer is arranged on the dielectric layer between the adjacent semiconductor devices and extends to two sides to part of the metal interconnection structure; A passivation layer disposed on the insulating layer; A first groove arranged on the surface of the metal interconnection structure and exposing part of the metal interconnection structure, and And a second groove surrounding the first groove and arranged on the metal interconnection structure, and exposing part of the insulating layer. In one embodiment of the present invention, the ratio between the annular width of the second groove and the depth of the inward depression of the second groove is (5-50): 1. In one embodiment of the present invention, a ratio between a distance between the first groove and the second groove and a depth of inward depression of the second groove is greater than 1. In an embodiment of the present invention, the thickness of the passivation layer is greater than 100nm, and the thickness of the insulating layer is less than the thickness of the passivation layer. The invention provides a preparation method of a semiconductor structure, which at least comprises the following steps: Providing a plurality of semiconductor devices arranged in parallel, wherein each semiconductor device at least comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, and the metal interconnection structure is arranged in a dielectric layer; Forming a second well region in the substrate between the first well regions of adjacent semiconductor devices; Forming an insulating layer on the dielectric layer between the adjacent semiconductor devices, wherein the insulating layer extends to two sides to part of the metal interconnection structure; forming a passivation layer on the insulating layer; Forming a first groove on the surface of the metal interconnection structure, wherein the first groove exposes part of the metal interconnection structure, and A second recess is formed on the metal interconnect structure surrounding the first recess, and the second recess exposes a portion of the insulating layer. In an embodiment of the present invention, when forming the first recess and the second recess, a first photoresist layer is first formed on the passivation layer, a first opening and a second opening are formed in the first photoresist layer, the first opening exposes a portion of the passivation layer on the metal interconnection structure, the second opening is disposed around the first opening and exposes a portion of the passivation layer on the metal interconnection structure, and a width of the first opening is greater than a ring width of the second opening. In an embodiment of the present invention, after the first opening and the second opening are formed, the first photoresist layer is used as a mask, the insulating layer under the first opening is used as an etching stop layer, the passivation layer exposed by the first opening and the second opening is etched to form a first concave portion and a second concave portion, the second concave portion is recessed inwards from the passivation layer to the surface of the insulating layer, and the first concave portion is disposed around the second concave portion and is re