Chip preparation method for reducing turn-off loss

Abstract

The invention provides a chip preparation method for reducing turn-off loss, which belongs to the technical field of chip preparation, and comprises the steps of carrying out multi-energy sectional ion implantation on a silicon substrate, determining the dose of each energy file by adopting a Monte Carlo prediction model, then carrying out pulse rapid thermal annealing treatment to control the diffusion distance, detecting the doping concentration distribution by a secondary ion mass spectrometer, calculating gradient kurtosis indexes by utilizing a carrier transport correction algorithm, inputting the gradient kurtosis indexes, peak concentration position offset and concentration distribution uniformity parameters into a process optimization prediction model to obtain annealing temperature correction values and implantation dose correction values, judging whether the gradient kurtosis indexes reach standards according to the correction values, and finally completing epitaxial growth, grid preparation and metallization treatment on the silicon substrate, thereby solving the technical problem that the gradient kurtosis of the doping concentration is difficult to accurately control and the turn-off loss of the chip is overhigh.

Inventors

WANG PILONG
TAN WENTAO
WANG YONGCHENG

Assignees

临沂大学

Dates

Publication Date: 20260508
Application Date: 20251225