CN-121805811-B - Grid loop inductance detection method for fault prediction

CN121805811BCN 121805811 BCN121805811 BCN 121805811BCN-121805811-B

Abstract

The invention relates to the technical field of fault prediction, and particularly discloses a grid loop inductance detection method for fault prediction, which comprises the following steps of collecting voltage signals of a grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing voltage waveforms according to the voltage values; counting the times of the rising edge Si which are larger than the preset stable high level and counting the times CS in all switching periods, counting the times of the falling edge Xi which are smaller than the preset stable low level and counting the times CX in all switching periods, calculating the rising time and the falling time based on voltage waveforms, averaging the rising slope and the average falling slope, calculating the rising index and the falling index, and judging the fault cause based on the rising index, the falling index, the times CS and the times CX. According to the invention, through counting the grid waveform characteristics of a plurality of switching periods, early fault identification and root cause distinction are realized, and the diagnosis accuracy and the system reliability are improved.

Inventors

SU YI
ZHANG YUE
YANG AIMIN
QIU LINTAO
ZHANG HONGWEI

Assignees

悦芯科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260309

Claims (5)

1. A gate loop inductance detection method for fault prediction, comprising the steps of: collecting voltage signals of the grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing voltage waveforms according to the voltage values; the method comprises the steps of obtaining rising edges Si and falling edges Xi in a voltage waveform of a switching period i, counting the times of the rising edges Si which are larger than a preset stable high level and counting the times CS in all switching periods; Calculating the rising time and the falling time of the switching period i based on the voltage waveform of the switching period i, and calculating the average rising slope and the average falling slope of the switching period i; Carrying out statistical distribution calculation on the average rising slope and the average falling slope of all the switching periods to obtain dispersion degree indexes of the average rising slope and the average falling slope, and respectively recording the dispersion degree indexes as rising indexes and falling indexes; Judging a fault reason based on the ascending index, the descending index, the times CS and the times CX, wherein the fault reason comprises parasitic inductance effect of a grid loop and insufficient loading capacity of a driving integrated circuit; the process for judging the fault cause comprises the following steps: when the rising index is greater than its preset threshold and the falling index is greater than its preset threshold: if CS is not equal to 0 and/or CX is not equal to 0, determining that the fault cause is parasitic inductance effect of the grid loop, and if CS=0 and CX=0, determining that the fault cause is insufficient loading capacity of the driving integrated circuit; and when the rising index is larger than the preset threshold value and the falling index is smaller than or equal to the preset threshold value or the rising index is smaller than or equal to the preset threshold value and the falling index is larger than the preset threshold value, judging that the failure cause is insufficient loading capacity of the driving integrated circuit.
2. The method for gate loop inductance detection for fault prediction as claimed in claim 1, wherein obtaining the voltage value comprises: Collecting voltage signals of the grid driving node in a plurality of continuous switching periods is achieved through a high-bandwidth voltage probe, the high-bandwidth voltage probe is connected to the grid driving node in a non-invasive mode, and analog voltage signals are captured; The analog voltage signal is converted into a voltage value by an analog-to-digital converter, the sampling rate of the analog-to-digital converter is set to be higher than the multiple of the switching frequency so as to ensure that the change details of the voltage signal are captured, the conversion process comprises the steps of sampling the analog voltage signal at equal intervals, generating a voltage value at each sampling point, and adding a corresponding time stamp, wherein the time stamps are synchronous based on a system clock.
3. The method of gate loop inductance detection for fault prediction as claimed in claim 2, wherein plotting the voltage waveform comprises: Generating data points in a coordinate system by taking the time stamp as a horizontal axis coordinate and the voltage value as a vertical axis coordinate, connecting adjacent data points through a smooth curve to form a continuous curve, thereby generating a voltage waveform, and carrying out smoothing on the voltage value to reduce noise influence, wherein a moving average method is adopted in the smoothing process, and the size of a window of the moving average is adjusted according to the sampling rate.
4. The method of claim 1, wherein calculating the up-and-down indicators comprises: Respectively calculating initial parameters of all average rising slopes and average falling slopes, wherein the initial parameters comprise variance, standard deviation and skewness; calculating a rising index based on the good-bad solution distance method and the initial parameters of the average rising slope; And calculating a descent index based on the good-bad solution distance method and the initial parameters of the average descent slope.
5. The method for gate loop inductance detection for fault prediction according to claim 1, further comprising, before determining a cause of the fault: if the ascending index and/or the descending index exceeds a preset reference range or the times CS and/or CX are/is larger than a preset times threshold, judging that a fault exists; if no fault exists, judging no fault reason; Wherein the reference ranges of the upper index and the lower index are different.

Description

Grid loop inductance detection method for fault prediction Technical Field The invention relates to the technical field of fault prediction, in particular to a grid loop inductance detection method for fault prediction. Background The grid loop is a special circuit for controlling the working state of the grid in the transistor or the electron tube so as to regulate and control the current of the main circuit. In failure analysis of switching power supplies, the delay of the rising or falling edge of the gate drive waveform is a typical phenomenon, and its conventional diagnostic path is usually directed to parasitic inductance effects of the gate loop. However, in practice there is a more concealed failure mechanism in which the actual load carrying capability of the driver integrated circuit is lower than its nominal parameters. The nature of the problem is that the "slow charge of gate capacitance" observed by the test is a comprehensive result. The peak current values noted in the driver chip manual are typically based on ideal conditions, which can compromise the true output capability under complex operating conditions. When the driving chip cannot output enough current, the charging and discharging processes of the grid capacitor are delayed, so that the residence time of the power switch tube in the linear region is directly prolonged. Therefore, how to accurately distinguish these two causes is a problem to be solved. Disclosure of Invention The invention aims to provide a grid loop inductance detection method for fault prediction, which solves the technical problems. The aim of the invention can be achieved by the following technical scheme: a gate loop inductance detection method for fault prediction, comprising the steps of: collecting voltage signals of the grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing voltage waveforms according to the voltage values; the method comprises the steps of obtaining rising edges Si and falling edges Xi in a voltage waveform of a switching period i, counting the times of the rising edges Si which are larger than a preset stable high level and counting the times CS in all switching periods; Calculating the rising time and the falling time of the switching period i based on the voltage waveform of the switching period i, and calculating the average rising slope and the average falling slope of the switching period i; Carrying out statistical distribution calculation on the average rising slope and the average falling slope of all the switching periods to obtain dispersion degree indexes of the average rising slope and the average falling slope, and respectively recording the dispersion degree indexes as rising indexes and falling indexes; And judging the fault reasons based on the rising index, the falling index, the times CS and the times CX, wherein the fault reasons comprise parasitic inductance effect of a grid loop and insufficient loading capacity of a driving integrated circuit. As a further aspect of the present invention, the obtaining the voltage value includes: Collecting voltage signals of the grid driving node in a plurality of continuous switching periods is achieved through a high-bandwidth voltage probe, the high-bandwidth voltage probe is connected to the grid driving node in a non-invasive mode, and analog voltage signals are captured; The analog voltage signal is converted into a voltage value by an analog-to-digital converter, the sampling rate of the analog-to-digital converter is set to be higher than the multiple of the switching frequency so as to ensure that the change details of the voltage signal are captured, the conversion process comprises the steps of sampling the analog voltage signal at equal intervals, generating a voltage value at each sampling point, and adding a corresponding time stamp, wherein the time stamps are synchronous based on a system clock. As a further aspect of the present invention, drawing the voltage waveform includes: Generating data points in a coordinate system by taking the time stamp as a horizontal axis coordinate and the voltage value as a vertical axis coordinate, connecting adjacent data points through a smooth curve to form a continuous curve, thereby generating a voltage waveform, and carrying out smoothing on the voltage value to reduce noise influence, wherein a moving average method is adopted in the smoothing process, and the size of a window of the moving average is adjusted according to the sampling rate. As a further aspect of the present invention, calculating the ascending index and the descending index includes: Respectively calculating initial parameters of all average rising slopes and average falling slopes, wherein the initial parameters comprise variance, standard deviation and skewness; calculating a rising index based on the good-bad solution distance method and the initial parameters of the average rising