CN-121805822-B - Hierarchical decision and intelligent control method for chip failure analysis path

CN121805822BCN 121805822 BCN121805822 BCN 121805822BCN-121805822-B

Abstract

The invention relates to the technical field of chip failure analysis, in particular to a hierarchical decision and intelligent control method of a chip failure analysis path, which comprises the steps of determining whether data optimization is performed according to a path abnormal frequency ratio of a target analysis model so as to obtain the optimized target analysis model; in the failure analysis supplementation, whether the outlier parameters are directly judged or whether the outlier parameters are secondarily judged according to the deviation repetition frequency secondary ratio and the parameter emerging coefficients are the outlier parameters is determined according to the related reference values, the data supplementation is carried out for each outlier parameter, and whether the global disturbance analysis supplementation is carried out is determined according to the global anomaly coefficients. The invention can improve analysis efficiency and result reliability.

Inventors

WANG SHIYING
HAN JIAN
WANG XIAOWEI
ZHAO GUOHAO

Assignees

长春慧程科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260309

Claims (10)

1. The hierarchical decision and intelligent control method for the chip failure analysis path is characterized by comprising the following steps of: Determining whether to perform data optimization according to the path anomaly frequency ratio of the target analysis model to obtain an optimized target analysis model; In the data optimization, a supplementary strategy of association data supplementation is adopted, and whether the supplementary strategy comprises failure analysis supplementation is determined according to the high-frequency association abnormal chip data duty ratio; in the associated data supplementation, supplementation is performed based on the abnormality detection parameters, and whether supplementation is performed based on the clustering contour coefficients of the fault probability map is determined based on the scattered data duty ratio; In failure analysis supplementation, determining whether an outlier parameter is directly judged according to a relevant reference value or secondarily judged according to a deviation repetition frequency sub-ratio and a parameter emerging coefficient, carrying out data supplementation on each outlier parameter, and determining whether global disturbance analysis supplementation is carried out according to a global anomaly coefficient; In the global disturbance analysis supplementation, supplementing data to be selected aiming at each design parameter with an abnormal reference value larger than a preset abnormal reference value, and determining whether to supplement based on a comparison reference mechanism according to discrete coefficients; and inputting the chip detection data of the failed chip into the optimized target analysis model to output sampling points and sampling point sequences.
2. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 1, wherein data optimization is performed on a target analysis model with a path anomaly frequency ratio greater than or equal to a preset path anomaly frequency ratio.
3. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 2, wherein if the high frequency associated abnormal chip data duty ratio is greater than or equal to a preset high frequency associated abnormal chip data duty ratio, the replenishment policy includes failure analysis replenishment; The high-frequency associated abnormal chip data are abnormal chip data with the associated failure chip duty ratio being larger than the preset associated failure chip duty ratio.
4. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 2, wherein when supplementing based on anomaly detection parameters, the anomaly detection parameters are determined based on parameter bias coefficients, and data to be selected are supplemented for each anomaly detection parameter according to sub-bias coefficients.
5. The hierarchical decision and intelligent control method for a chip failure analysis path according to claim 4, wherein if the scattered data duty ratio is greater than or equal to a preset scattered data duty ratio, the method is based on a clustering contour coefficient of a fault probability map for supplementing; the scattered data are abnormal chip data with the clustering contour coefficient of the fault probability map larger than the preset clustering contour coefficient.
6. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 2, wherein the design parameters with the correlation reference value greater than or equal to the preset correlation reference value are directly determined as outlier parameters; And secondarily judging whether the design parameter is an outlier parameter according to the deviation recurrence frequency order ratio and the parameter emerging coefficient aiming at the design parameter with the correlation reference value smaller than the preset correlation reference value, wherein if the deviation recurrence frequency order ratio of the design parameter is larger than or equal to the preset deviation recurrence frequency order ratio and the parameter emerging coefficient is larger than or equal to the preset parameter emerging coefficient, the design parameter is marked as the outlier parameter.
7. The hierarchical decision and intelligent control method for a chip failure analysis path according to claim 6, wherein the method for confirming the deviation from the recurrence frequency ratio comprises: fitting based on span coefficients and parameter deviation corresponding to each design parameter to obtain a fitting curve; Determining fitting deviation degree of each design parameter under corresponding abnormal chip data according to the corresponding parameter deviation degree of the span coefficient on the fitting curve and the actual parameter deviation degree of the design parameter; And determining the deviation recurrence frequency ratio of the corresponding design parameters based on the ratio of the number of abnormal chip data with the fitting deviation degree smaller than the preset fitting deviation degree to the total number of the abnormal chip data.
8. The hierarchical decision-making and intelligent control method for a chip failure analysis path according to claim 1, wherein if the global anomaly coefficient is greater than or equal to a predetermined global anomaly coefficient, global disturbance analysis is performed.
9. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 8, wherein the supplementing is based on a comparison reference mechanism if the discrete coefficient is greater than or equal to a preset discrete coefficient.
10. The hierarchical decision and intelligent control method of a chip failure analysis path according to claim 9, wherein when supplementing based on a comparison reference mechanism, supplementing is performed for each comparison reference mechanism, and the number of data to be selected, which are supplemented for a single comparison reference mechanism, and a comparison coefficient corresponding to the comparison reference mechanism are in a positive correlation relationship; The comparison reference mechanism is a reference mechanism with a comparison coefficient larger than a preset comparison coefficient, and the reference mechanism is an associated failure mechanism corresponding to data of each abnormal chip.

Description

Hierarchical decision and intelligent control method for chip failure analysis path Technical Field The invention relates to the technical field of chip failure analysis, in particular to a hierarchical decision and intelligent management and control method of a chip failure analysis path. Background Along with the continuous improvement of chip integration level and circuit complexity, the chip failure mode is diversified and complicated, failure analysis is used as a core link for improving the chip yield, positioning failure sources and optimizing chip design and production processes, and the analysis efficiency and path decision accuracy have key influences on cost control and cycle shortening of chip research and development and mass production. The traditional decision-making mode which completely depends on the manual experience of a senior engineer is replaced by a dependent model, so that the analysis efficiency is improved, but due to the complexity of chip production, model data supplement lacks targeting, quantitative characterization of failure characteristics is incomplete, and the suitability of the model data supplement to the systematic characteristics of actual chip failure is insufficient. Therefore, how to improve the reliability of model prediction, further improve the overall efficiency of chip failure analysis, and reduce the cost of analysis error test and sample loss is a technical problem to be solved by those skilled in the art. Chinese patent publication No. CN114076881A discloses a failure analysis method, a device, equipment and a storage medium of a semiconductor device, wherein the method comprises the steps of obtaining target detection parameters of a normal semiconductor device through physical detection, wherein the target detection parameters comprise detection parameters of a failure point area on the normal semiconductor device, which correspond to the failure point area, on the failure semiconductor device, the surface detection parameters of the failure point area, element concentration detection parameters of the failure point area and profile detection parameters of the failure point area, inputting the obtained target detection parameters as input parameters of a preset simulation algorithm, and predicting failure results through the combination of the preset simulation algorithm, so as to obtain failure reasons of the failure semiconductor device. However, the scheme has the following problems that the failure cause is deduced by only acquiring normal device parameters through physical detection and combining a simulation algorithm, dynamic data optimization of an analysis model is lacked, and the analysis design is not supplemented in a targeting manner, so that the analysis efficiency and the result reliability are poor. Disclosure of Invention Therefore, the invention provides a hierarchical decision and intelligent control method of a chip failure analysis path, which is used for solving the problems of poor analysis efficiency and result reliability caused by lack of dynamic data optimization of an analysis model and no targeting supplementary analysis design in the prior art. In order to achieve the above objective, the present invention provides a hierarchical decision and intelligent control method for a chip failure analysis path, including: Determining whether to perform data optimization according to the path anomaly frequency ratio of the target analysis model to obtain an optimized target analysis model; In the data optimization, a supplementary strategy of association data supplementation is adopted, and whether the supplementary strategy comprises failure analysis supplementation is determined according to the high-frequency association abnormal chip data duty ratio; in the associated data supplementation, supplementation is performed based on the abnormality detection parameters, and whether supplementation is performed based on the clustering contour coefficients of the fault probability map is determined based on the scattered data duty ratio; In failure analysis supplementation, determining whether an outlier parameter is directly judged according to a relevant reference value or secondarily judged according to a deviation repetition frequency sub-ratio and a parameter emerging coefficient, carrying out data supplementation on each outlier parameter, and determining whether global disturbance analysis supplementation is carried out according to a global anomaly coefficient; In the global disturbance analysis supplementation, supplementing data to be selected aiming at each design parameter with an abnormal reference value larger than a preset abnormal reference value, and determining whether to supplement based on a comparison reference mechanism according to discrete coefficients; and inputting the chip detection data of the failed chip into the optimized target analysis model to output sampling points and sampling point sequences. Further, da