CN-121809380-B - Sigma-Delta modulator design method, system and equipment based on 180nm process

CN121809380BCN 121809380 BCN121809380 BCN 121809380BCN-121809380-B

Abstract

The invention belongs to the technical field of integrated circuit design, and particularly relates to a design method, a system and equipment of a Sigma-Delta modulator based on a 180nm process, wherein firstly, the noise transfer function of the modulator is parameterized to minimize in-band quantization noise power, and meanwhile, stability and realizability composite constraint is applied; optimizing under constraint conditions by adopting a covariance matrix strategy to obtain an optimal transfer function and a feedforward coefficient, designing a switched capacitor circuit based on the coefficient, shaping random mismatch noise to be out of band through a high-pass dithering signal modulation cycle selection logic, estimating and compensating inherent bias of each capacitor based on quantizer output, and breaking periodic locking to inhibit coherent straying. The invention realizes the tight connection of theoretical design and physical realization, and has excellent voltage and temperature robustness.

Inventors

NING YAFEI
HE XI
XU HAO
ZHANG LICHAO
QU JIANBO

Assignees

山东大学

Dates

Publication Date: 20260505
Application Date: 20260306

Claims (10)

1. The design method of the Sigma-Delta modulator based on the 180nm process mainly comprises a loop filter, a quantizer and a feedback digital-to-analog converter circuit, wherein the loop filter comprises quantization noise, signal transmission and noise transmission, and the design method is characterized by comprising the following steps: s1, pole-zero parameterization is carried out on a noise transfer function of a modulator, and a noise transfer function parameterization expression is obtained; S2, quantizing in-band noise power through integration parameterized by a noise transfer function, establishing an objective function, and applying power gain upper limit constraint and voltage upper limit constraint to the noise transfer function; S3, acquiring all candidate solutions enabling the objective function to be established, establishing an adaptability function based on the objective function, the power gain upper limit constraint and the voltage upper limit constraint, setting a search center, a search step length and a covariance matrix to search all the candidate solutions, calculating adaptability functions corresponding to the searched candidate solutions, carrying out feasibility sequencing according to the adaptability functions corresponding to the searched candidate solutions, updating the search center, the search step length and the covariance matrix based on sequencing results, repeatedly executing the search process based on the updated search center, the search step length and the covariance matrix until convergence conditions are met, and taking the search center as pole configuration expressed by parameterization of a noise transfer function when the convergence conditions are met to obtain a final noise transfer function; s4, constructing a dithering signal in each clock cycle in the existing N capacitors, and updating a selection pointer based on the dithering signal; calculating an error proxy signal of each capacitor, estimating the deviation of each capacitor according to the error proxy signal of each capacitor to obtain a deviation estimated value, and mapping the deviation estimated value to a selection weight; For all the capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to the selection weight of the capacitors, so that a final noise transfer function is realized, and the modulator design is completed.
2. The method of claim 1, wherein the step S4 of updating the selection pointer based on the dither signal is: , , Wherein, the For a limited de-correlation delay, For the sampling instant, ρ is a fixed step size, δn is the dither signal, In order to perform a modulo operation on N, For the binary selection vector generated at sample time n, An initial window function that contains M successive selected capacitances.
3. The method of claim 1, wherein the step S4 is performed by estimating the bias of each capacitor according to the error proxy signal of each capacitor to obtain a bias estimate: , Wherein, the For the deviation estimate of the ith capacitor at sample time n +1, For the deviation estimate of the ith capacitor at sample time n, In order to learn the step size of the step, As an error proxy signal, For the selected state of the ith capacitor at sample time n, The number of capacitors selected for each clock cycle, For the number of capacitors included in the array, Is a small amount of orthogonal disturbance and, Is the sampling instant.
4. The method of claim 1, wherein S4 is characterized in that for all capacitors, M capacitors are selected in parallel by updated selection pointers according to their selection weights, specifically, a cumulative usage counter is established for each capacitor, the number of times the capacitor has been selected in the current clock cycle is recorded, the updated selection pointer is moved forward by one bit per clock cycle, for the currently pointed capacitor, if the cumulative usage counter < selection weight, the capacitor is selected, if the cumulative usage counter is greater than or equal to the selection weight, the capacitor is skipped, the pointer continues to move, and is repeated until M capacitors are selected, and the parallel connection circuit achieves the final noise transfer function, thereby completing the modulator design.
5. The method for designing a Sigma-Delta modulator based on a 180nm process according to claim 1, wherein the upper limit constraint of voltage in S2 is that a state space model of output voltage is established based on a feedforward coefficient parametrically expressed by a noise transfer function, an input signal capable of enabling the voltage of an integrator inside the modulator to reach the maximum amplitude is set, and the state space model is subjected to time domain simulation to obtain the output voltage as the upper limit constraint of voltage.
6. The method of designing a Sigma-Delta modulator based on a 180nm process according to claim 1, wherein the step of S2 is to parameterize the integral expressed in the signal band by the noise transfer function, quantize the in-band noise power, and establish the objective function by: , Wherein, the As a function of the object to be processed, Representing the normalized cut-off frequency of the signal band, Representing the frequency weighting function, Representing the noise transfer function at frequency The power gain at x is the decision vector.
7. A base according to claim 1, 180 Sigma-Delta modulator design method for nm process, the method is characterized in that the fitness function in S3 is specifically as follows: , Wherein, the In order to adapt the function of the degree of adaptation, As an objective function, when the constraints A1, A2, A3 are satisfied, = The constraints A1, A2 and A3 are respectively the upper limit constraint of the power gain, With solution, upper voltage limit constraints, other conditions = , Feedforward coefficients parametrically expressed for noise transfer function, transform matrix , In order to optimize the coefficient of the coefficients, Is an objective function.
8. The method for designing a Sigma-Delta modulator according to claim 1, wherein the upper power gain constraint in S2 is specifically: , Wherein, the Representing the maximum absolute value of the noise transfer function, In order for the amplitude-frequency response to be of interest, Is a predetermined stability interval constant.
9. A Sigma-Delta modulator design system based on a 180nm process for implementing a Sigma-Delta modulator design method based on a 180nm process as claimed in any of claims 1-8, comprising: the parameterization module is used for carrying out pole-zero parameterization on the noise transfer function of the modulator to obtain parameterized expression of the noise transfer function; The constraint module quantifies in-band noise power through the integration parameterized by the noise transfer function and establishes an objective function, and applies power gain upper limit constraint and voltage upper limit constraint to the noise transfer function; The noise transfer function solving module is used for acquiring all candidate solutions enabling the objective function to be established, establishing an adaptability function based on the objective function, the power gain upper limit constraint and the voltage upper limit constraint, setting a search center, a search step length and a covariance matrix to search all candidate solutions, calculating adaptability functions corresponding to the searched candidate solutions, carrying out feasibility sequencing according to the adaptability functions corresponding to the searched candidate solutions, updating the search center, the search step length and the covariance matrix based on sequencing results, repeatedly executing the search process based on the updated search center, the search step length and the covariance matrix until convergence conditions are met, and taking the search center meeting the convergence conditions as pole configuration expressed by parameterization of the noise transfer function to obtain a final noise transfer function; the capacitor selection module is used for constructing a dithering signal in each clock cycle in the existing N capacitors and updating a selection pointer based on the dithering signal; calculating an error proxy signal of each capacitor, estimating the deviation of each capacitor according to the error proxy signal of each capacitor to obtain a deviation estimated value, and mapping the deviation estimated value to a selection weight; For all the capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to the selection weight of the capacitors, so that a final noise transfer function is realized, and the modulator design is completed.
10. A Sigma-Delta modulator design method device based on a 180nm process, comprising a processor and a memory, wherein the processor implements a Sigma-Delta modulator design method based on a 180nm process as claimed in any of claims 1-8 when executing a computer program stored in the memory.

Description

Sigma-Delta modulator design method, system and equipment based on 180nm process Technical Field The invention belongs to the technical field of integrated circuit design, and particularly relates to a design method, a system and equipment of a Sigma-Delta modulator based on a 180nm process. Background In modern integrated circuit designs, high-precision analog-to-digital converters are the core components that connect the physical world with digital signal processing. The analog-to-digital converter can realize high-bandwidth internal resolution under moderate clock frequency and power consumption by means of oversampling and noise shaping technology, and is widely applied to the field of low-bandwidth sensing. In various topological structures with discrete time, the feedback integrator cascade architecture can reduce the signal swing of an internal node and keep a signal transfer function close to unit gain, so that the requirements on the margin and linearity of an operational amplifier are relaxed, and the feedback integrator cascade architecture becomes an ideal choice of a compact and high-energy-efficiency sensor readout circuit. The prior art still faces two technical bottlenecks, namely, firstly, the comprehensive design difficulty of a noise transfer function is extremely high, a pole-zero is required to be manually configured through a tool box, but when a high-order loop is faced, extremely strong nonlinear coupling relation exists between pole-zero parameters, so that the manual tuning is difficult to reproduce and extremely depends on experience. Second, the component mismatch problem in the switched capacitor circuit can seriously affect the accuracy of the modulator, especially when the input signal is close to direct current or is a slow-changing signal, the nonlinear error is easily converted into obvious harmonic distortion and in-band spurious, and the signal-to-noise distortion ratio of the modulator is seriously lowered. Disclosure of Invention The invention aims to provide a design method, a system and equipment of a Sigma-Delta modulator based on a 180nm process. A design method of a Sigma-Delta modulator based on a 180nm process mainly comprises a loop filter, a quantizer and a feedback digital-to-analog converter circuit, wherein the loop filter comprises a quantization noise function, a signal transfer function and a noise transfer function, and the design method comprises the following steps: s1, pole-zero parameterization is carried out on a noise transfer function of a modulator, and a noise transfer function parameterization expression is obtained; S2, quantizing in-band noise power through integration parameterized by a noise transfer function, establishing an objective function, and applying power gain upper limit constraint and voltage upper limit constraint to the noise transfer function; S3, acquiring all candidate solutions enabling the objective function to be established, establishing an adaptability function based on the objective function, the power gain upper limit constraint and the voltage upper limit constraint, setting a search center, a search step length and a covariance matrix to search all the candidate solutions, calculating adaptability functions corresponding to the searched candidate solutions, carrying out feasibility sequencing according to the adaptability functions corresponding to the searched candidate solutions, updating the search center, the search step length and the covariance matrix based on sequencing results, repeatedly executing the search process based on the updated search center, the search step length and the covariance matrix until convergence conditions are met, and taking the search center as pole configuration expressed by parameterization of a noise transfer function when the convergence conditions are met to obtain a final noise transfer function; s4, constructing a dithering signal in each clock cycle in the existing N capacitors, and updating a selection pointer based on the dithering signal; calculating an error proxy signal of each capacitor, estimating the deviation of each capacitor according to the error proxy signal of each capacitor to obtain a deviation estimated value, and mapping the deviation estimated value to a selection weight; For all the capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to the selection weight of the capacitors, so that a final noise transfer function is realized, and the modulator design is completed. In S4, updating the selection pointer based on the dithering signal, specifically: , , Wherein, the For a limited de-correlation delay,For the sampling instant, ρ is a fixed step size, δn is the dither signal,In order to perform a modulo operation on N,For the binary selection vector generated at sample time n,An initial window function that contains M successive selected capacitances. S4, estimating the deviation of each capacitor according to