CN-121833570-B - Scheduling circuit, data stream scheduling method and electronic equipment

Abstract

The application provides a scheduling circuit, a data stream scheduling method and electronic equipment, wherein the scheduling circuit comprises a first scheduler used for scheduling a first request data stream initiated by a remote chip, a second scheduler used for scheduling a first response data stream and a second response data stream returned to a local chip, a third scheduler used for scheduling a first scheduling result of the first scheduler and a second scheduling result of the second scheduler and circulating the second request data stream and the second response data stream to a fourth scheduler, and a fourth scheduler used for scheduling the second request data stream, the second response data stream, a third request data stream initiated by the local chip and the third response data stream. According to the application, different types of data streams can be efficiently scheduled.

Inventors

• WU ZHIJING
• ZHAO CHANGHE

Assignees

• 上海东方算芯科技有限公司

Dates

Publication Date

20260512

Application Date

20260312

Claims (10)

1. 1. A scheduling circuit, the scheduling circuit comprising: The first scheduler is used for scheduling the first request data stream initiated by the remote chip; The second scheduler is used for performing scheduling processing on a first response data stream and a second response data stream returned to the local end chip, the local end chip and the remote end chip are interconnected through a preset bus system, the second response data stream is a scheduling node and a data stream returned to the remote end chip by the local end preset bus system, and the scheduling node is a logic module at the same level with the scheduling circuit; The third scheduler is used for performing scheduling processing on a first scheduling result of the first scheduler and a second scheduling result of the second scheduler, and streaming a second request data stream and the second response data stream back to the fourth scheduler, wherein the second request data stream is a data stream of a request initiated by the far-end chip to the scheduling node and the local preset bus system; the fourth scheduler is configured to perform scheduling processing on the second request data stream, the second response data stream, a third request data stream initiated by the local end chip, and a third response data stream, where the third response data stream is a data stream returned by the local end chip to the remote end chip.
2. 2. The scheduling circuit of claim 1, further comprising a first buffer, wherein: the first buffer is configured to buffer the first response data stream and a fourth request data stream, where the fourth request data stream is a data stream that the remote chip initiates a request to the local chip; The first buffer is further configured to parse the first response data stream and the fourth request data stream, and send the parsed first response data stream and the parsed fourth request data stream to the local chip.
3. 3. The scheduling circuit of claim 1, further comprising a first decoder, a second buffer, and a third buffer, wherein: the second buffer is used for buffering the data stream of the request type; the third buffer is configured to buffer a data stream of a response type; The first decoder is configured to decode a fourth scheduling result of the fourth scheduler, and determine a data stream type of each data stream in the fourth scheduling result, where the data stream type is a request type or a response type; The first decoder is further configured to store a data stream of a request type in the fourth scheduling result to the second buffer, and store a data stream of a response type in the fourth scheduling result to the third buffer.
4. 4. A scheduling circuit according to claim 3 wherein the scheduling circuit further comprises a second decoder, wherein: The second decoder is configured to perform target port analysis on the data stream in the second buffer to obtain target port information; the second decoder is further configured to send the data stream in the second buffer to a destination port corresponding to the destination port information.
5. 5. A scheduling circuit according to claim 3 wherein the scheduling circuit further comprises a third decoder, wherein: the third decoder is configured to perform source end analysis on the data stream in the third buffer to obtain source end information; the third decoder is further configured to send the data stream in the third buffer to a source end corresponding to the source end information.
6. 6. The scheduling circuit of any one of claims 1 to 5, wherein the first request data stream comprises a data stream that the remote chip initiates a request to the local chip, a data stream that the remote chip initiates a request to the scheduling node, and a data stream that the remote chip initiates a request to the local preset bus system.
7. 7. The scheduling circuit of any one of claims 1 to 5, wherein the first response data stream comprises a data stream returned by the scheduling node to the home chip, a data stream returned by a remote preset bus system to the home chip, and a data stream returned by the remote chip to the home chip.
8. 8. The scheduling circuit of any one of claims 1 to 5, wherein the third request data stream includes a data stream from which the local chip initiates a request to the scheduling node, a data stream from which the local chip initiates a request to a remote preset bus system, and a data stream from which the local chip initiates a request to the remote chip.
9. 9. A data flow scheduling method, characterized in that the method is applied to the scheduling circuit of any one of claims 1 to 8, the method comprising: Scheduling a first request data stream initiated by a remote chip through a first scheduler; The method comprises the steps that a first response data stream and a second response data stream returned to a local end chip are scheduled through a second scheduler, the local end chip and the remote end chip are interconnected through a preset bus system, the second response data stream is a scheduling node and a data stream returned to the remote end chip by the local end preset bus system, and the scheduling node is a logic module at the same level with the scheduling circuit; Scheduling the first scheduling result of the first scheduler and the second scheduling result of the second scheduler through a third scheduler, and streaming a second request data stream and the second response data stream back to a fourth scheduler, wherein the second request data stream is a data stream of a request initiated by the far-end chip to the scheduling node and the local preset bus system; And carrying out scheduling processing on the second request data stream, the second response data stream, a third request data stream initiated by the local chip and a third response data stream by the fourth scheduler, wherein the third response data stream is the data stream returned to the remote chip by the local chip.
10. 10. An electronic device, characterized in that it comprises the scheduling circuit of any one of claims 1 to 8.

Description

Scheduling circuit, data stream scheduling method and electronic equipment Technical Field The present application relates to the field of digital circuits, and in particular, to a scheduling circuit, a data stream scheduling method, and an electronic device. Background In modern electronic systems, particularly in the fields of high-performance computing, artificial intelligence, the internet of things and the like, multi-chip systems are increasingly used. These systems are typically composed of a plurality of functionally distinct chips, such as a central processing unit, a graphics processor, a digital signal processor, and various application specific integrated circuits. Efficient collaboration between different chips is critical to overall system performance, while data flow scheduling is a key technique to ensure that this collaboration works well. In complex scenarios such as artificial intelligence and large data processing, where data needs to be frequently transmitted and processed among multiple chips, optimized data flow scheduling can ensure the efficiency and reliability of these operations, supporting more complex tasks and higher loads. In the related art, a crossbar bridge (Crossbar Bridge IP) is adopted to schedule data streams, because redundancy characteristics supported by the crossbar bridge are more and part of redundancy characteristics cannot be cut, chip area is wasted, register transmission level (REGISTER TRANSFER LEVEL, RTL) codes of the crossbar bridge are subjected to encryption processing or script generation, so that problem positioning efficiency is low when the crossbar bridge is utilized for simulation. Disclosure of Invention The embodiment of the application provides a scheduling circuit, a data stream scheduling method and electronic equipment, which can be used for efficiently scheduling different types of data streams. The technical scheme of the embodiment of the application is realized as follows: the embodiment of the application provides a scheduling circuit, which comprises: The first scheduler is used for scheduling the first request data stream initiated by the remote chip; The second scheduler is used for performing scheduling processing on a first response data stream and a second response data stream returned to the local end chip, the local end chip and the remote end chip are interconnected through a preset bus system, the second response data stream is a scheduling node and a data stream returned to the remote end chip by the local end preset bus system, and the scheduling node is a logic module at the same level with the scheduling circuit; The third scheduler is used for performing scheduling processing on a first scheduling result of the first scheduler and a second scheduling result of the second scheduler, and streaming a second request data stream and the second response data stream back to the fourth scheduler, wherein the second request data stream is a data stream of a request initiated by the far-end chip to the scheduling node and the local preset bus system; the fourth scheduler is configured to perform scheduling processing on the second request data stream, the second response data stream, a third request data stream initiated by the local end chip, and a third response data stream, where the third response data stream is a data stream returned by the local end chip to the remote end chip. The embodiment of the application provides a data flow scheduling method, which comprises the following steps: Scheduling a first request data stream initiated by a remote chip through a first scheduler; The method comprises the steps that a first response data stream and a second response data stream returned to a local end chip are scheduled through a second scheduler, the local end chip and the remote end chip are interconnected through a preset bus system, the second response data stream is a scheduling node and a data stream returned to the remote end chip by the local end preset bus system, and the scheduling node is a logic module at the same level with the scheduling circuit; Scheduling the first scheduling result of the first scheduler and the second scheduling result of the second scheduler through a third scheduler, and streaming a second request data stream and the second response data stream back to a fourth scheduler, wherein the second request data stream is a data stream of a request initiated by the far-end chip to the scheduling node and the local preset bus system; And carrying out scheduling processing on the second request data stream, the second response data stream, a third request data stream initiated by the local chip and a third response data stream by the fourth scheduler, wherein the third response data stream is the data stream returned to the remote chip by the local chip. The embodiment of the application provides electronic equipment, which comprises the scheduling circuit provided by the embodiment of the application. T