CN-121841079-B - Full-range optimized modulation method for three-level inverter bus capacitor current

CN121841079BCN 121841079 BCN121841079 BCN 121841079BCN-121841079-B

Abstract

The invention discloses a full-range optimized modulation method for three-level inverter bus capacitor current, which realizes the suppression of DC bus capacitor current ripple and prolongs the service life of the capacitor by systematically identifying and replacing small vectors which lead to large ripple current in the traditional SVPWM. The invention realizes the effective suppression of the high-frequency current ripple wave of the DC bus capacitor in the full modulation range and the full power factor angle range of the TNPC type three-phase three-level inverter, can solve the problem from the source of generating the capacitor current ripple wave through simple software programming, does not need to introduce extra hardware cost, relaxes the requirement on the type selection of the DC bus supporting capacitor, does not need to select a large-capacity capacitor allowing the ripple current to be large, reduces the volume of equipment, improves the power density, and greatly prolongs the prediction service life of the DC bus supporting capacitor.

Inventors

XU QIANMING
Xu Malong
TANG CHENG
GUO PENG
REN SHAOWEI
HAN YI
WANG ZETONG
ZHOU XIAOPING
HONG LERONG

Assignees

湖南大学

Dates

Publication Date: 20260508
Application Date: 20260313

Claims (7)

1. The full-range optimized modulation method for the three-level inverter bus capacitor current is characterized by comprising the following steps of: Analyzing midpoint current amplitude values corresponding to different switch states of the three-level inverter, identifying a target small vector which can introduce maximum phase current to a midpoint and generate the highest midpoint current ripple, and taking the target small vector which can introduce the maximum phase current to a neutral point and generate the highest midpoint current ripple as a core object for subsequent virtual small vector replacement and reconstruction; step B, carrying out sector reconstruction on a space vector diagram of the three-level inverter, dividing the space vector diagram into six large sectors on average, dividing each large sector into four small sectors on average, realizing fine matching of reference voltage vectors, determining sector matching rules, and guaranteeing that expected reference voltage vectors can be synthesized linearly and without distortion within a modulation degree range of 0-1; Step C, detecting power factor angles of the three-level inverter, and matching corresponding virtual small vector synthesis modes aiming at different power factor angle ranges, wherein the virtual small vector synthesis modes meet the following requirements: firstly) synthesizing virtual small vectors by paired basic voltage vectors with opposite effects on midpoint potential in equal proportion, secondly) synthesizing the synthesized virtual small vectors into expected reference voltage vectors accurately by a volt-second balance principle, and thirdly) introducing current to a neutral point as the minimum value in three-phase current of a current sector when the synthesized virtual small vectors act so as to realize maximum suppression of midpoint current ripple; Step D, redesigning a vector action sequence according to the virtual small vector synthesis mode selected in the step C, calculating the action time of each basic vector, ensuring smooth switching of the switch, avoiding P-N state jump and minimizing the switching times; e, designing driving PWM signals of each power switch device according to the vector action sequence designed in the step D; The specific steps of the step B are as follows: B1, dividing a space vector diagram into 6 large sectors according to an SVPWM method, and reconstructing each large sector into 4 small sectors from 6 small sectors, wherein one large sector comprises a virtual zero vector VVZ, a first virtual small vector VVS1, a second virtual small vector VVS2, a virtual middle vector VVM, a first virtual large vector VVL1 and a second virtual large vector VVL2; The method comprises the steps of B2 judging a small sector where a reference voltage vector is located, and synthesizing the reference voltage vector by using three adjacent virtual vectors, wherein the method comprises the steps of synthesizing the reference voltage vector by using VVS1, VVVZ and VVM in a first small sector A1, synthesizing the reference voltage vector by using VVS2, VVZ and VVM in a second small sector A2, synthesizing the reference voltage vector by using VVS1, VVM and VVL1 in a third small sector A3, and synthesizing the reference voltage vector by using VVS2, VVM and VVL2 in a fourth small sector A4; the specific steps of the step C are as follows: Step C1, a first virtual small vector VVS1 and a second virtual small vector VVS2 are synthesized by using two basic voltage vectors with opposite effects on midpoint potential, wherein three synthesis modes with different contributions on midpoint current amplitude are adopted, the first induced midpoint current amplitude of the vector synthesis mode is I Ib I, the second induced midpoint current amplitude of the vector synthesis mode is I Ic I, the third induced midpoint current amplitude of the vector synthesis mode is I Ia I, I Ib I and I Ic I respectively represent three-phase load current amplitude at the current moment, a virtual zero vector VVZ is a basic zero vector VOOO, a virtual middle vector VVM is a basic middle vector VPON, and the first virtual large vector VVL1 and the second virtual large vector VVL2 are basic large vectors VPNN and VPPN; step C2, judging the load type, and switching the synthesis strategy of the first virtual small vector VVS1 and the second virtual small vector VVS2 aiming at different power factor angles to enable the midpoint current flowing through the neutral point to be the minimum value in the three-phase current of the current sector; in the step C2, a vector synthesis mode III is used in the range of the power factor angle (-5 pi/12, -pi/6), a vector synthesis mode I is used in the range of the power factor angle (-pi/6, pi/6), a vector synthesis mode II is used in the range of the power factor angle (pi/6, 5 pi/12), and a synthesis strategy of SVPWM method is used in the ranges of the power factor angles (-pi/2, -5 pi/12) and (5 pi/12, pi/2); in the first vector synthesis method: Wherein, P represents the P state, namely the state that the output voltage u XO of the inverter is 0.5u dc , u dc is the DC power supply voltage, O state is the state that the output voltage u XO of the inverter is 0, N state is the state that the output voltage u XO of the inverter is-0.5 u dc ; a substantially zero vector representing three-phase switching states OOO, i.e., A, B, C three phases connected to a neutral point (O); a basic midvector representing a three-phase switching state PON, i.e. a phase a connected to a positive busbar (P), a phase B connected to a neutral point (O), and a phase C connected to a negative busbar (N); a basic small vector representing the three-phase switch state ONO, i.e. A, C connected to neutral (O), B connected to negative busbar (N); A basic small vector representing the three-phase switching state OPO, i.e. A, C connected to the neutral point (O), B connected to the positive busbar (P); A basic large vector representing three-phase switching states PNN, i.e. a phase a connected to a positive busbar (P), B, C connected to a negative busbar (N); a basic large vector representing three-phase switching states PPN, i.e. A, B phases connected to the positive bus (P), C connected to the negative bus (N); In the second vector synthesis mode: Wherein, the Representing the three-phase switching state as PNO, namely, the A phase is connected to a positive bus (P), the B phase is connected to a negative bus (N), and the C phase is connected to a basic middle vector of a neutral point (O); A basic small vector representing a three-phase switching state OON, i.e., A, B connected to neutral (O), C connected to negative bus (N); a basic small vector representing the three-phase switching state PPO, i.e. A, B phases connected to the positive busbar (P), C connected to the neutral point (O); In the third vector synthesis method: Wherein, the Representing the three-phase switching state as POO, i.e. the basic small vector with phase A connected to the positive busbar (P), phase B, C connected to the neutral point (O), Representing a basic small vector with three-phase switching states ONN, i.e. phase a connected to neutral (O), phase B, C connected to negative busbar (N), Representing the three-phase switching state as OPN, i.e. the basic midvector with a phase connected to the neutral point (O), B phase connected to the positive busbar (P), C phase connected to the negative busbar (N).
2. The full-range optimized modulation method of three-level inverter bus capacitor current according to claim 1, wherein in the step a, the quantitative relationship between the dc bus capacitor current and the midpoint current is as follows: Wherein iC1 represents capacitor current on the DC bus, iC2 represents capacitor current under the DC bus, inp represents midpoint current; the target small vector which can introduce the maximum phase current to the neutral point and generate the highest midpoint current ripple is the small vector nearest to the reference voltage vector in the SVPWM method.
3. The full-range optimized modulation method of three-level inverter bus capacitor current according to claim 1, wherein the vector action sequence of the corresponding vector synthesis mode one of the four small sectors is as follows: A1:[PON]-[OOO]-[ONO]-[OOO]-[PON]; A2:[PON]-[OOO]-[OPO]-[OOO]-[PON]; A3:[PON]-[PNN]-[ONO]-[PNN]-[PON]; A4:[PON]-[PPN]-[OPO]-[PPN]-[PON]; the vector action sequence of the corresponding vector synthesis mode II of the four small sectors is as follows: A1:[OOO]-[OON]-[PON]-[PNO]-[PON]-[OON]-[OOO]; A2:[OOO]-[OON]-[PON]-[PPO]-[PON]-[OON]-[OOO]; A3:[OON]-[PON]-[PNN]-[PNO]-[PNN]-[PON]-[OON]; A4:[OON]-[PON]-[PPN]-[PPO]-[PPN]-[PON]-[OON]; the vector action sequence of the corresponding vector synthesis mode three of the four small sectors is as follows: A1:[OOO]-[POO]-[PON]-[ONN]-[PON]-[POO]-[OOO]; A2:[OOO]-[POO]-[PON]-[OPN]-[PON]-[POO]-[OOO]; A3:[POO]-[PON]-[PNN]-[ONN]-[PNN]-[PON]-[POO]; A4:[POO]-[PON]-[PPN]-[OPN]-[PPN]-[PON]-[POO]。
4. The full-range optimized modulation method for bus capacitor current of three-level inverter according to claim 1, wherein in said step D, the vector action sequence follows the following principle: D1, when the switching state is switched from P to N or N to P, transition is needed through the state O, so that the inverter is prevented from being seriously damaged by the direct connection of a switching tube; And D2, preferentially selecting a vector action sequence with fewer switching times of each phase of switch.
5. The full-range optimized modulation method of the three-level inverter bus capacitor current according to claim 1, wherein in the step E, the required modulation wave signals are calculated according to the vector action sequence and the vector action time, carrier signals of different sections are calculated, and the modulation wave signals are compared with the carrier signals to output PWM signals, so as to realize the control of the switching tube.
6. The full-range optimized modulation method of three-level inverter bus capacitor current according to claim 1, wherein the three-level inverter is a T-type inverter, an NPC-type inverter, or a hybrid ANPC inverter.
7. The full-range optimized modulation method of bus capacitor current of three-level inverter of claim 6, wherein said three-level inverter is a T-type inverter comprising a DC power supply (U dc ), the positive electrode of the DC power supply (U dc ) is electrically connected with one end of an upper capacitor (C 1 ), the drain electrode of an A switch tube I (S a1 ), the drain electrode of a B switch tube I (S b1 ) and the drain electrode of a C switch tube I (S c1 ); The negative electrode of the direct current power supply (U dc ) is electrically connected with one end of a lower capacitor (C 2 ), the source electrode of an A switch tube IV (S a4 ), the source electrode of a B switch tube IV (S b4 ) and the source electrode of a C switch tube IV (S c4 ), and the other end of an upper capacitor (C 1 ) and the other end of a lower capacitor (C 2 ) are electrically connected with a neutral point (O); The neutral point (O) is electrically connected with the drain electrode of the switch tube A II (S a2 ), the drain electrode of the switch tube B II (S b2 ) and the drain electrode of the switch tube C II (S c2 ); The source electrode of the switch tube II (S a2 ) is electrically connected with the source electrode of the switch tube III (S a3 ), the drain electrode of the switch tube III (S a3 ) is electrically connected with the source electrode of the switch tube I (S a1 ) and one end of the A-phase filter inductor, and the other end of the A-phase filter inductor is electrically connected with the A-phase end of the load; The source electrode of the second switching tube (S b2 ) is electrically connected with the source electrode of the third switching tube (S b3 ), the drain electrode of the third switching tube (S b3 ) is electrically connected with the source electrode of the first switching tube (S b1 ) and one end of the B-phase filter inductor, and the other end of the B-phase filter inductor is electrically connected with the B-phase end of the load; The source electrode of the second C switch tube (S C2 ) is electrically connected with the source electrode of the third C switch tube (S c3 ), the drain electrode of the third C switch tube (S c3 ) is electrically connected with the source electrode of the first C switch tube (S c1 ) and one end of the C-phase filter inductor, and the other end of the C-phase filter inductor is electrically connected with the C-phase end of the load.

Description

Full-range optimized modulation method for three-level inverter bus capacitor current Technical Field The invention belongs to the technical field of power electronics, and particularly relates to a full-range optimized modulation method for high-frequency current ripple of a direct-current bus capacitor of a three-phase three-level inverter. Background The three-level NPC inverter is widely applied to middle and high power occasions such as wind power generation, photovoltaic grid connection, energy storage systems and the like due to the advantages of the three-level NPC inverter in the aspects of output voltage harmonic characteristics, device withstand voltage grades and the like. Such inverters typically require the use of capacitors to stabilize the dc bus voltage, absorb ripple current. The electrolytic capacitor has wide application in DC bus by virtue of low cost and large capacitance per unit volume. The volume, weight and life of power electronic converters are often limited by the dc bus support capacitance. However, electrolytic capacitors have a high Equivalent Series Resistance (ESR), and high frequency current ripple flowing through the capacitor causes losses, resulting in increased core temperature of the capacitor, increased internal self-heating, and increased ESR. In addition, the electrolytic capacitor has weak resistance to electrothermal stress, and the stress accelerates volatilization of electrolyte, so that the capacity of the capacitor is reduced. When the capacitance drops to 80% of the existing value or ESR doubles, it is generally considered to be the end of the electrolytic capacitor's operating life. In order to relieve the burden caused by the stress, a large-capacity capacitor with large allowable ripple current is required to be selected, or a capacitor series connection mode is adopted, but the schemes all cause the increase of the system volume and the increase of the cost. Therefore, the optimized suppression of the capacitor current ripple is important to improve the reliability of the direct current bus supporting capacitor, prolong the service life of the capacitor, reduce the volume of the device and improve the power density of the device. However, the existing three-phase inverter modulation method is not suitable for a three-level converter, has insufficient suppression effect on capacitive current ripple, and can only optimize the capacitive current ripple under a specific modulation degree or power factor angle. Disclosure of Invention In order to solve the problems, the invention provides a full-range optimal modulation method for the bus capacitor current of a three-level inverter. A full-range optimized modulation method for three-level inverter bus capacitor current comprises the following steps: Analyzing the midpoint current amplitude values corresponding to different switch states of the three-level inverter, identifying a target small vector which can introduce the maximum phase current to a neutral point and generate the highest midpoint current ripple, and taking the target small vector which can introduce the maximum phase current to the neutral point and generate the highest midpoint current ripple as a core object for subsequent virtual small vector replacement and reconstruction; step B, carrying out sector reconstruction on a space vector diagram of the three-level inverter, dividing the space vector diagram into six large sectors on average, dividing each large sector into four small sectors on average, realizing fine matching of reference voltage vectors, determining sector matching rules, and guaranteeing that expected reference voltage vectors can be synthesized linearly and without distortion within a modulation degree range of 0-1; Step C, detecting power factor angles of the three-level inverter, and matching corresponding virtual small vector synthesis modes aiming at different power factor angle ranges, wherein the virtual small vector synthesis modes meet the following requirements: firstly) synthesizing virtual small vectors by paired basic voltage vectors with opposite effects on midpoint potential in equal proportion, secondly) synthesizing the synthesized virtual small vectors into expected reference voltage vectors accurately by a volt-second balance principle, and thirdly) introducing current to a neutral point as the minimum value in three-phase current of a current sector when the synthesized virtual small vectors act so as to realize maximum suppression of midpoint current ripple; Step D, redesigning a vector action sequence according to the virtual small vector synthesis mode selected in the step C, calculating the action time of each basic vector, ensuring smooth switching of the switch, avoiding P-N state jump and minimizing the switching times; and E, designing driving PWM signals of the power switching devices according to the vector action sequence designed in the step D. In a further improvement, in the step a, the quan