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CN-121971800-A - Low power buffer circuit for neuron stimulation

CN121971800ACN 121971800 ACN121971800 ACN 121971800ACN-121971800-A

Abstract

The invention discloses a low-power-consumption buffer circuit for neuron stimulation, which belongs to the technical field of microelectronics and comprises a neuron model, a current driving module, a buffer stage operational amplifier and a feedback resistor network, wherein the neuron model is used for simulating the electrical characteristics of biological neurons, the input end of the neuron model is connected with a node WE of the current driving module, the output end of the neuron model is connected with a node RE, the current driving module is used for generating current stimulation pulses under the control of enabling signals and providing the current stimulation pulses to the input end of the neuron model for electric stimulation, the buffer stage operational amplifier is used for stabilizing the port voltage of the neuron model at the node RE and comprises an amplifying stage, a biasing stage, a current buffering stage, an output stage and an auxiliary current stimulation stage, and the feedback resistor network is used for sampling the voltage from the node RE and providing the feedback voltage to the buffer stage operational amplifier after voltage division. The invention realizes the high-performance buffer circuit with low power consumption, prolongs the standby time, saves the area cost of the chip and is beneficial to integration.

Inventors

  • LIU LIANXI
  • DAI YUXUAN
  • LIU XIANGYI
  • ZHANG YINUO
  • LIAO XUFENG
  • ZHOU CHENGHAO
  • ZHU ZHANGMING

Assignees

  • 西安电子科技大学重庆集成电路创新研究院

Dates

Publication Date
20260505
Application Date
20260113

Claims (10)

  1. 1. A low-power-consumption buffer circuit for neuron stimulation is characterized by comprising a neuron model, a current driving module, a buffer level operational amplifier and a feedback resistor network, wherein, The neuron model is used for simulating the electrical characteristics of biological neurons, the input end of the neuron model is connected with a node WE of the current driving module, and the output end of the neuron model is connected with a node RE; the current driving module is used for generating current stimulation pulses under the control of an enabling signal and providing the current stimulation pulses to the input end of the neuron model for electric stimulation; the buffer level operational amplifier is used for stabilizing the port voltage of the neuron model at the node RE; the feedback resistor network is used for sampling voltage from the node RE and providing feedback voltage for the buffer stage operational amplifier after voltage division.
  2. 2. The low power buffer circuit for neuron stimulation according to claim 1, wherein the neuron model comprises a capacitor C 1 and a resistor R 5 、R 6 , wherein the capacitor C 1 is connected in series with the resistor R 5 and then in parallel with the resistor R 6 .
  3. 3. The low power buffer circuit for neuron stimulation according to claim 2, wherein the current driving module comprises a pulse current source I pulse1 、I pulse2 and an enable switch S 1 、S 2 , wherein enable switch S 1 is connected in series between I pulse1 and the node WE, enable switch S 2 is connected in series between I pulse2 and the node WE, enable switch S 1 、S 2 is connected to enable signals EN 1 and EN 2 , respectively.
  4. 4. The low power buffer circuit for neuron stimulation according to claim 2, wherein the buffer stage operational amplifier comprises an amplification stage, a bias stage, a current buffer stage, an output stage, and an auxiliary current stimulation stage, wherein, The amplifying stage is used for providing gain required by the current buffer stage; The bias stage is used for providing bias voltage for each transistor in the amplifying stage; the current buffer stage is used for converting a voltage jitter signal input by the inverting input end from a low-voltage domain to a high-voltage domain; The output stage is used for providing stable port voltage for the node RE; The auxiliary current stimulus stage is for assisting the output stage in outputting a current required to stimulate the neuron model under control of enable signals EN 1 and EN 2 .
  5. 5. The low power buffer circuit for neuron stimulation according to claim 4, wherein the low power buffer circuit comprises a low voltage power supply V BAT , the amplifier stage comprises NMOS transistors M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 and M 13 and PMOS transistors M 9 、M 10 、M 11 、M 12 and M 14 , wherein, M and the source end of M are connected with the drain end of M, the gate end of M is connected with the reverse input end, the gate end of M is connected with the forward input end, the source end of M is connected with the drain end of M, the source end of M is grounded, the gate ends of M are connected with the drain end of M and the source end of M, the drain end of M is connected with the drain end of M and the source end of M, the source ends of M are both connected with the gate end of M, the gate end of M is connected with the gate end of M, the drain end of M is connected with the drain end of M and the gate end of M, the drain end of M is connected with the drain end of M, the source end of M is connected with the drain end of M, and the source end of M is grounded.
  6. 6. The low power buffer circuit for neuron stimulation according to claim 5, wherein the bias stage comprises a current source I 1 、I 2 , an NMOS tube M 19 、M 20 and a PMOS tube M 17 、M 18 , wherein, The gate end of M 17 , the drain end of M 17 and the positive end of current source I 1 are connected with the gate end of M 11 , the gate end of M 18 , the drain end of M 18 are connected with the gate end of M 9 , the source end of M 18 and the positive end of current source I 2 are connected with the gate end of low-voltage power supply V BAT ;M 19 , the drain end of M 19 and the negative end of current source I 2 are connected with the gate end of M 3 , the source end of M 19 , the gate end of M 20 and the drain end of M 20 are connected with the gate end of M 4 , and the source end of M 20 and the negative end of current source I 1 are grounded.
  7. 7. The low power buffer circuit for neuron stimulation according to claim 6, wherein the current buffer stage comprises an NMOS tube M 16 , a PMOS tube M 15 and a high voltage conversion unit, wherein, The gate end of M 15 is connected with the drain end of M 12 , the source end of M 15 is connected with the drain end of the low-voltage power supply V BAT ,M 15 and is connected with the output stage, the gate end of M 16 is connected with the source end of M 13 , the source end of M 16 is grounded, and the drain end of M 16 is connected with the input end of the high-voltage conversion unit.
  8. 8. The low power buffer circuit for neuron stimulation according to claim 7, wherein the high voltage conversion unit comprises a PMOS tube M 29 and an NMOS tube M 30 , wherein, The drain terminal of M 29 is connected to the gate terminal of M 29 、M 30 and the source terminal of the low voltage source V BAT ,M 29 is connected to the source terminal of M 30 and the drain terminal of M 16 , and the drain terminal of M 30 is connected to the drain terminal of M 21 and the gate terminal of M 21 .
  9. 9. The low power buffer circuit for neuron stimulation according to claim 7, further comprising a high voltage power supply V OUT,LDO , wherein the output stage comprises a PMOS tube M 21 、M 23 and an NMOS tube M 22 、M 24 , wherein, The gate end and the drain end of M 21 , the gate end of M 23 and the gate end of M 24 are connected with the output end of the high-voltage conversion unit, the source end of M 21 、M 23 is connected with the drain end of the high-voltage power supply V OUT,LDO ,M 22 , the gate end of M 22 and the gate end of M 24 are connected with the drain end of M 15 , the source end of M 22 is grounded, the source end of M 23 is connected with the drain end of the high-voltage power supply V OUT,LDO ,M 23 and the drain end of M 24 , the source end of M 24 is grounded, and the drain end of M 24 is connected with the drain end of M 23 and the node RE.
  10. 10. The low power buffer circuit for neuron stimulation according to claim 9, further comprising a high voltage power supply V OUT,LDO , wherein the auxiliary current stimulation stage comprises a PMOS tube M 25 、M 26 and an NMOS tube M 27 M 28 , wherein, The gate end of M 25 and the gate end of M 28 are connected with the output end of the high-voltage conversion unit, the source end of M 25 is connected with the drain end of the high-voltage power supply V OUT,LDO ,M 25 and is connected with the source end of M 26 , the drain end of M 26 is connected with the drain end of M 24 , the gate end of M 26 is connected with the drain end of the enable signal EN 2 ;M 27 and is connected with the drain end of M 24 , the gate end of M 27 is connected with the source end of the enable signal EN 1 ,M 27 and is connected with the drain end of M 28 , the gate end of M 28 is connected with the drain end of M 15 , and the source end of M 28 is grounded.

Description

Low power buffer circuit for neuron stimulation Technical Field The invention belongs to the technical field of microelectronics, and particularly relates to a low-power-consumption buffer circuit for neuron stimulation. Background Brain diseases are not only important challenges facing health in China, but also prominent problems in the health field worldwide. In recent years, with the continuous progress of microelectronic technology, an implantable brain-computer interface (Implantable BCI) has become an important direction of global scientific research as an emerging field based on microelectronic technology, converged biomedical science, wireless communication and computer technology. Among them, the neurostimulator is regarded as a key component for realizing accurate neuromodulation, which applies high-frequency electrical stimulation to a specific nerve region by implanting electrodes in the deep brain, thereby modulating abnormal nerve activity and improving clinical symptoms of patients. However, since the device is typically an implantable device, the power management issues are particularly acute. The existing implanted chemical battery has a series of problems of limited battery capacity, high risk of replacement operation, difficult guarantee of long-term safety and the like, so that the service life of equipment is prolonged, and the replacement frequency of the battery is reduced to be an urgent requirement in practical application. Disclosure of Invention In order to solve the above-mentioned problems in the prior art, the present invention provides a low power buffer circuit for neuron stimulation. The technical problems to be solved by the invention are realized by the following technical scheme: The invention provides a low-power consumption buffer circuit for neuron stimulation, which comprises a neuron model, a current driving module, a buffer level operational amplifier and a feedback resistor network, wherein, The neuron model is used for simulating the electrical characteristics of biological neurons, the input end of the neuron model is connected with a node WE of the current driving module, and the output end of the neuron model is connected with a node RE; the current driving module is used for generating current stimulation pulses under the control of an enabling signal and providing the current stimulation pulses to the input end of the neuron model for electric stimulation; the buffer level operational amplifier is used for stabilizing the port voltage of the neuron model at the node RE; the feedback resistor network is used for sampling voltage from the node RE and providing feedback voltage for the buffer stage operational amplifier after voltage division. In one embodiment of the invention, the neuron model comprises a capacitor C 1 and a resistor R 5、R6, wherein the capacitor C 1 is connected in series with the resistor R 5 and then connected in parallel with the resistor R 6. In one embodiment of the invention, the current driving module comprises a pulse current source I pulse1、Ipulse2 and an enable switch S 1、S2, wherein the enable switch S 1 is connected in series between I pulse1 and the node WE, the enable switch S 2 is connected in series between I pulse2 and the node WE, and the enable switch S 1、S2 is respectively connected with enable signals EN 1 and EN 2. In one embodiment of the invention, the buffer stage operational amplifier comprises an amplifying stage, a biasing stage, a current buffer stage, an output stage and an auxiliary current stimulus stage, wherein, The amplifying stage is used for providing gain required by the current buffer stage; The bias stage is used for providing bias voltage for each transistor in the amplifying stage; the current buffer stage is used for converting a voltage jitter signal input by the inverting input end from a low-voltage domain to a high-voltage domain; The output stage is used for providing stable port voltage for the node RE; The auxiliary current stimulus stage is for assisting the output stage in outputting a current required to stimulate the neuron model under control of enable signals EN 1 and EN 2. In one embodiment of the invention, the low power buffer circuit comprises a low voltage power supply V BAT, the amplifying stage comprises NMOS transistors M 1、M2、M3、M4、M5、M6、M7、M8 and M 13 and PMOS transistors M 9、M10、M11、M12 and M 14, wherein, M and the source end of M are connected with the drain end of M, the gate end of M is connected with the reverse input end, the gate end of M is connected with the forward input end, the source end of M is connected with the drain end of M, the source end of M is grounded, the gate ends of M are connected with the drain end of M and the source end of M, the drain end of M is connected with the drain end of M and the source end of M, the source ends of M are both connected with the gate end of M, the gate end of M is connected with the gate end of M, the drain end of M is conn