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CN-121973750-A - Monitoring device and vehicle speed reducer

CN121973750ACN 121973750 ACN121973750 ACN 121973750ACN-121973750-A

Abstract

The invention discloses a monitoring device and a vehicle speed reducer, wherein the monitoring device is applied to the vehicle speed reducer and comprises an oil pressure sensor, a temperature sensor and an acquisition extension set, wherein the oil pressure sensor is used for acquiring oil pressure in a hydraulic station originally matched with the vehicle speed reducer and then sending the oil pressure to the acquisition extension set, the temperature sensor is used for acquiring oil temperature in the hydraulic station originally matched with the vehicle speed reducer and then sending the oil temperature to the acquisition extension set, the acquisition extension set is respectively connected with the oil pressure sensor and the temperature sensor and used for receiving the oil pressure data uploaded by the oil pressure sensor and the oil temperature data uploaded by the temperature sensor and then uploading the oil temperature data to an external computer, and the acquisition extension set comprises a plurality of external interfaces, a plurality of signal processing circuits, a power carrier processing circuit, a core processing circuit and a power supply circuit. The invention has scientific design, can safely and reliably monitor the braking state (the braking pressure and the oil temperature of hydraulic oil) on the vehicle speed reducer, and ensures the operation safety of the vehicle speed reducer.

Inventors

  • LIU HONGFEI
  • FU GUANGYU
  • YAN XINGGUO
  • CHI XU
  • Yue Zixiong

Assignees

  • 天津铁路信号有限责任公司

Dates

Publication Date
20260505
Application Date
20260310

Claims (10)

  1. 1. The monitoring device is characterized by comprising an oil pressure sensor (1), a temperature sensor (2) and a collecting extension (3); the oil pressure sensor (1) is used for collecting oil pressure in a hydraulic station originally matched with the vehicle speed reducer and then sending the oil pressure to the collecting extension (3); the temperature sensor (2) is used for acquiring the oil temperature in the hydraulic station originally matched with the vehicle speed reducer and then sending the oil temperature to the acquisition extension (3); The collecting extension (3) is respectively connected with the oil pressure sensor (1) and the temperature sensor (2) and is used for receiving the oil pressure data uploaded by the oil pressure sensor (1) and the oil temperature data uploaded by the temperature sensor (2) and then uploading the oil pressure data to an external computer; the acquisition extension (3) comprises a plurality of external interfaces, a plurality of signal processing circuits, a power carrier processing circuit (319), a core processing circuit (320) and a power supply circuit (321); a plurality of external interfaces respectively connected with the plurality of signal processing circuits, the power carrier processing circuit (319) and the core processing circuit (320); the plurality of signal processing circuits are connected with the core processing circuit (320); a core processing circuit (320) connected to the power carrier processing circuit (319); and a power supply circuit (321) connected to the plurality of external interfaces, the plurality of signal processing circuits, the power carrier processing circuit (319), and the core processing circuit (320), respectively.
  2. 2. The monitoring device of claim 1, wherein the plurality of external interfaces specifically comprises a first external interface unit (301), a second external interface (302), a third external interface (303), a fourth external interface (304), a fifth external interface (305), a sixth external interface (306), a seventh external interface (307), an eighth external interface (308), a ninth external interface (309), and a tenth external interface (310); The first external interface (301), the second external interface (302), the third external interface (303), the fourth external interface (304), the fifth external interface (305), the sixth external interface (306), the seventh external interface (307), the eighth external interface (308) and the tenth external interface (310) are all four-pin aviation sockets; wherein the ninth external interface (309) is a three pin aviation socket; The plurality of signal processing circuits comprise two analog signal processing circuits, two 485 signal processing circuits, two I2C signal processing circuits and two UART signal processing circuits; The two analog signal processing circuits specifically comprise a first analog signal processing circuit (311) and a second analog signal processing circuit (312) which are respectively and correspondingly connected with a first external interface (301) and a second external interface (302); The two 485 signal processing circuits specifically comprise a first 485 signal processing circuit (313) and a second 485 signal processing circuit (314) which are respectively and correspondingly connected with a third external interface (303) and a fourth external interface (304); The two I2C signal processing circuits specifically comprise a first I2C signal processing circuit (315) and a second I2C signal processing circuit (316), which are correspondingly connected with a fifth external interface (305) and a sixth external interface (306) respectively; The two UART signal processing circuits specifically comprise a first UART signal processing circuit (317) and a second UART signal processing circuit (318) which are respectively and correspondingly connected with a seventh external interface (307) and an eighth external interface (308); The ninth external interface (309) is connected to the core processing circuit (320) through the power carrier communication processing circuit (313); and a core processing circuit (320) connected to the tenth external interface (310).
  3. 3. A monitoring device according to claim 2, characterized in that the first analog signal processing circuit (311) in the collecting extension (3) comprises a U1 chip; the U1 chip comprises two operational amplifiers U1A and U1B; the VCC end of the U1 chip is connected with a first direct current power end 12V-1; the GND end of the U1 chip is connected with GND; the non-inverting input end of the operational amplifier U1A is respectively connected with one ends of the resistors R2 and R4; The other end of the resistor R4 is connected with GND; the other end of the resistor R2 is respectively connected with one end of the resistor R1 and the 2 nd pin of the first external interface (301); the inverting input end of the operational amplifier U1A is respectively connected with one end of a resistor R3 and one end of a resistor R5; the other end of the resistor R3 is connected with GND; the inverting input end of the operational amplifier U1A is also connected with the output end out of the operational amplifier U1A through resistors R5 and R6; the output end out of the operational amplifier U1A is connected with the non-inverting input end of the operational amplifier U1B through a resistor R7; the non-inverting input end of the operational amplifier U1B is connected with GND through a resistor R8; The inverting input end of the operational amplifier U1B is connected with GND through a resistor R10; The inverting input end of the operational amplifier U1B is also connected with the output end out of the operational amplifier U1B through a resistor R9; the output end out of the operational amplifier U1B is an ADC1 end and is connected with the ADC1 end of the chip U10 in the core processing circuit (320); And/or the number of the groups of groups, A first 485 signal processing circuit (313) in the acquisition extension (3) comprises a U2 chip; The R end of the U2 chip is an RXD1 end, and the R end is connected with the RXD1 end of the U10 chip in the core processing circuit (320) and one end of the resistor R14; the other end of the resistor R14 is connected with a second direct current power supply end 3.3V-2; The RE end of the U2 chip is connected with the DE end; The collector of the triode Q1 is connected with the DE end of the U2 chip; The emitter of the triode Q1 is connected with GND; the base electrode of the triode Q1 is connected with one end of a resistor R12; The DE end of the U2 chip is connected with one end of a resistor R13; The other end of the resistor R13 is connected with a second direct current power supply end 3.3V-2; The second direct current power supply end 3.3V-2 is connected with one end of the resistor R11; The other end of the resistor R11 is a TXD1 end which is connected with the TXD1 end of the U10 chip in the core processing circuit (320); the D end of the U2 chip is connected with GND; the VCC end of the U2 chip is connected with the second direct current power supply end 3.3V-2; The A end of the U2 chip is connected with the 2 nd pin of the third external interface (303) The B end of the U2 chip is connected with a3 rd pin of a third external interface (303); The GND end of the U2 chip is connected with GND; the VCC end of the U2 chip is connected with one end of a resistor R15; The other end of the resistor R15 is connected with the end A of the U2 chip; The end A of the U2 chip is connected with one end of a resistor R16; the other end of the resistor R16 is connected with the end B of the U2 chip; The end B of the U2 chip is connected with one end of a resistor R17; the other end of the resistor R17 is connected to the GND terminal.
  4. 4. The monitoring device according to claim 2, characterized in that the first I2C signal processing circuit (315) in the acquisition extension (3) comprises a resistor R46; One end of the resistor R46 is connected with the second direct current power supply end 3.3V-2; the other end of the resistor R46 is an SDA1 end, and the resistor R46 is connected with the SDA1 end of the U10 chip in the core processing circuit (320); One end of the resistor R47 is connected with the second direct current power supply end 3.3V-2; the other end of the resistor R47 is an SCK1 end, and the SCK1 end of the U10 chip in the core processing circuit (320) is connected with the SCK1 end; And/or the number of the groups of groups, A first UART signal processing circuit 317 in the acquisition extension (3) including an optocoupler U4; the VDD2 end of the optical coupler U4 is connected with the 1 st pin of the seventh external interface (307); the VDD1 end of the optical coupler U4 is connected with the second direct current power supply end 3.3V-2; the VIB end of the optical coupler U4 is connected with a2 nd pin of a seventh external interface (307); the VOA end of the optical coupler U4 is connected with a3 rd pin of a seventh external interface (307); the GND1 end and the GND2 end of the optical coupler U4 are grounded; the VOB end and the VIA end of the optocoupler U4 are respectively RXD3 and TXD3 ends, and are respectively connected with the RXD3 and TXD3 ends of the U10 chip in the core processing circuit (320).
  5. 5. The monitoring device of claim 1, wherein the power supply circuit (321) comprises an AC220V-DC12V circuit, a DC12V isolation circuit, a DC12V-5V circuit, a first DC12V-3.3V circuit, a second DC12V-3.3V circuit, and a voltage selection circuit; The AC220V-DC12V circuit comprises an alternating current-to-direct current power supply module U5; The L end of the alternating current-to-direct current power supply module U5 is connected with the 1 st pin of the ninth external interface (309) through an inductor L1; the N end of the ac-dc power module U5 is connected to the 2 nd pin of the ninth external interface 309 through the inductor L2; the 12V end of the alternating current-to-direct current power supply module U5 is respectively connected with one ends of the capacitors C6, C7 and C8; The 12V end of the alternating current-to-direct current power supply module U5 is connected with the 12V-1 end of the first direct current power supply; the GND end of the alternating current-to-direct current power supply module U5 is respectively connected with the other ends of the capacitors C6, C7 and C8; The GND end of the AC-DC power module U5 is grounded.
  6. 6. The monitoring device of claim 5, wherein the first DC12V-3.3V circuit comprises a DC voltage regulator chip U6; the VIN pin of the direct current voltage stabilizing chip U6 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit; the EN end of the direct current voltage stabilizing chip U6 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit through a resistor R21; The SW end of the direct current voltage stabilizing chip U6 is connected with one end of the inductor L3; the other end of the inductor L3 is respectively connected with one end of the resistor R22, one end of the capacitor C11 and one end of the capacitor C12; The other end of the inductor L3 is also connected with a third direct current power supply end 3.3V-1; The other ends of the capacitors C11 and C12 are connected with the GND end of the direct-current voltage stabilizing chip U6; The FB end of the direct current voltage stabilizing chip U6 is respectively connected with the other end of the resistor R22 and one end of the resistor R23; The other end of the resistor R23 is connected with the GND end of the direct-current voltage stabilizing chip U6; the GND end of the direct-current voltage-stabilizing chip U6 is grounded; The VIN end of the direct-current voltage stabilizing chip U6 is grounded through a capacitor C9; the SW end and the CB end of the direct current voltage stabilizing chip U6 are respectively connected with the two ends of the capacitor C10; And/or the number of the groups of groups, The second DC12V-3.3V circuit comprises a direct current voltage stabilizing chip U7 and a field effect transistor Q2; The VIN pin of the direct current voltage stabilizing chip U7 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit; the EN end of the direct current voltage stabilizing chip U6 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit through a resistor R26; the drain electrode of the field effect transistor Q2 is connected with the EN end of the direct current voltage stabilizing chip U7 through a resistor R26; the grid electrode of the field effect transistor Q2 is connected with one ends of the resistors R24 and R25; the source electrode of the field effect transistor Q2 is respectively connected with the other end of the resistor R25; the other end of the resistor R25 is grounded to GND; the other end of the resistor R24 is a RST1 end which is connected with a RST1 signal end of the U10 chip in the core processing circuit (320); the SW end and the CB end of the direct current voltage stabilizing chip U7 are respectively connected with the two ends of the capacitor C14; the SW end of the direct current voltage stabilizing chip U7 is connected with one end of the inductor L4; the other end of the inductor L4 is respectively connected with one end of a resistor R27, one end of a capacitor C15 and one end of a capacitor C16; the other end of the inductor L4 is also connected with a second direct current power supply end 3.3V-2; The other ends of the capacitors C15 and C16 are connected with the GND end of the direct-current voltage stabilizing chip U7; the FB end of the direct current voltage stabilizing chip U7 is connected with the other end of the resistor R27 and one end of the resistor R28; the other end of the resistor R28 is connected with the GND end of the direct-current voltage stabilizing chip U7; The GND end of the direct-current voltage-stabilizing chip U7 is grounded; And/or the number of the groups of groups, The DC12V-5V circuit comprises a direct current voltage stabilizing chip U8 and a field effect transistor Q3; the VIN pin of the direct current voltage stabilizing chip U8 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit; the EN end of the direct current voltage stabilizing chip U8 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit through a resistor R31; the drain electrode of the field effect transistor Q3 is connected with the EN end of the direct current voltage stabilizing chip U8 through a resistor R31; The grid electrode of the field effect transistor Q3 is connected with one ends of the resistors R29 and R30; the source electrode of the field effect transistor Q3 is respectively connected with the other end of the resistor R30; The other end of the resistor R30 is grounded to GND; The other end of the resistor R29 is a RST2 end which is connected with a RST2 signal end of the U10 chip in the core processing circuit (320); The SW end and the CB end of the direct current voltage stabilizing chip U8 are respectively connected with the two ends of the capacitor C18; the SW end of the direct current voltage stabilizing chip U8 is connected with one end of the inductor L5; the other end of the inductor L5 is respectively connected with one end of a resistor R32, one end of a capacitor C19 and one end of a capacitor C20; the other end of the inductor L5 is also connected with a fourth direct current power supply end; The other ends of the capacitors C19 and C20 are connected with the GND end of the direct-current voltage stabilizing chip U8; The FB end of the direct current voltage stabilizing chip U8 is connected with the other end of the resistor R32 and one end of the resistor R33; The other end of the resistor R33 is connected with the GND end of the direct-current voltage stabilizing chip U8; The GND end of the direct-current voltage-stabilizing chip U8 is grounded; And/or the number of the groups of groups, The DC12V isolation circuit comprises a direct current voltage stabilizing chip U9 and a field effect transistor Q4; The VIN pin of the direct current voltage stabilizing chip U9 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit; The EN end of the direct current voltage stabilizing chip U9 is connected with a first direct current power supply end 12V-1 in an AC220V-DC12V circuit through a resistor R36; The drain electrode of the field effect transistor Q4 is connected with the EN end of the direct current voltage stabilizing chip U9 through a resistor R36; the grid electrode of the field effect transistor Q4 is connected with one ends of the resistors R34 and R35; The source electrode of the field effect transistor Q4 is respectively connected with the other end of the resistor R35; the other end of the resistor R35 is grounded to GND; the other end of the resistor R34 is a RST3 end which is connected with a RST3 signal end of the U10 chip in the core processing circuit (320); the SW end of the direct current voltage stabilizing chip U9 is connected with one end of the inductor L6; the other end of the inductor L6 is respectively connected with one end of a resistor R37, one end of a capacitor C23 and one end of a capacitor C24; the other end of the inductor L6 is also connected with a fifth direct current power supply end 12-2; the other ends of the capacitors C23 and C24 are connected with the GND end of the direct-current voltage stabilizing chip U9; the FB end of the direct current voltage stabilizing chip U9 is connected with the other end of the resistor R37 and one end of the resistor R38; the other end of the resistor R38 is connected with the GND end of the direct-current voltage stabilizing chip U9; the GND end of the direct-current voltage stabilizing chip U9 is grounded.
  7. 7. The monitoring device of claim 5, wherein the DC12V isolation circuit comprises switches K1 and K2; two input ends of the switch K1 are respectively connected with a second direct current power supply end 3.3V-2; The input end of the switch K1 is connected with the 1 st pin of the seventh external interface (307); Two input ends of the switch K2 are respectively connected with the second direct current power supply end 3.3V-2; the input end of the switch K2 is connected with the 1 st pin of the eighth external interface (308).
  8. 8. The monitoring device according to any of claims 1 to 7, characterized by a core processing circuit (320) in the acquisition extension, comprising a chip U10; the VCC end of the chip U10 is connected with the third direct current power supply end 3.3V-1; GND of the chip U10 is grounded to GND; the RXD1 end and the TXD1 end of U10 are respectively connected with the RXD1 end and the TXD1 end in the first 485 signal processing circuit (313), The RXD2 end and the TXD2 end of the chip U10 are respectively connected with the RXD2 end and the TXD2 end in the second 485 signal processing circuit (314); The RXD3 end and the TXD3 end of the chip U10 are respectively connected with the RXD3 end and the TXD3 end in the first UART signal processing circuit (317), The RXD4 end and the TXD4 end of the chip U10 are respectively connected with the RXD4 end and the TXD4 end in the second UART signal processing circuit (318); the SDA1 end and the SCK1 end of the chip U10 are respectively connected with the SDA1 end and the SCK1 end in the first I2C signal processing circuit (315); the SDA2 end and the SCK2 end of the chip U10 are respectively connected with the SDA2 end and the SCK2 end in the second I2C signal processing circuit (316); the TXD0 and RXD0 ends of the chip U10 are respectively connected with the 2 nd pin and the 3 rd pin in the tenth external interface (310); the ADC1 end of the chip U10 is connected with the ADC1 end in the first analog signal processing circuit (311); the ADC1 end of the chip U10 is connected with the ADC2 end in the second analog signal processing circuit (312); The TX1P-L, TX1N-L, RX1P-L and RX1N-L ends of the chip U10 are respectively and correspondingly connected with the TX1P-L, TX1N-L, RX1P-L and RX1N-L ends in the power carrier processing circuit 319; The EN end of the chip U10 is connected with the RESET end of the chip U11; The GPIO0 end of the chip U10 is connected with the WDI end of the chip U11; the VCC end of U11 is connected with a first direct current power end 12V-1; GND of U11 is grounded to GND; the GPIO1 end of the chip U10 is connected with the RST1 end in the power circuit (320); the GPIO2 end of the chip U10 is connected with the RST2 end in the power circuit (320); The GPIO3 terminal of the chip U10 is connected with the RST3 terminal in the power circuit (320).
  9. 9. The monitoring device according to claim 1, wherein the power carrier communication processing circuit (319) in the acquisition extension comprises a power carrier module U13; The VCC end of U13 is connected with the fourth direct current power supply end; GND of U13 is grounded to GND; the PLC0+ end of U13 is connected with the 2 nd pin of the ninth external interface (309) through a resistor R42 and a capacitor C27; The PLC 0-end of U13 is connected with one end of a resistor R43, The PLC1+ end of U13 is connected with one end of a resistor R44; The other ends of the resistors R43 and R44 are connected with the 1 st pin of the ninth external interface (309) through the other end of the capacitor C28 after the confluence intersection; the PLC 1-end of the U13 is connected with a3 rd pin of a ninth external interface (309) through a resistor R45 and a capacitor C29; The power carrier communication processing circuit 319 further comprises a network port transformer chip U12; the TX+ end of U12 is connected with the TX0+ end of U13; the TX-end of U12 is connected with the TX 0-end of U13; The RX+ end of U12 is connected with the RX0+ end of U13; the RX-end of U12 is connected with the RX 0-end of U13; the CT3 end and the CT4 end of the U12 are respectively connected with one ends of the resistors R40 and R41; the other ends of the resistors R40 and R41 are connected with one end of the capacitor C26; the other end of the capacitor C26 is grounded to GND; After the ends CT1 and CT2 of the U12 are converged and intersected, the ends CT1 and CT2 of the U12 are connected with one end of a resistor R39 and one end of a capacitor C25; The other end of the resistor R39 is connected with the second direct current power supply end 3.3V-2; the other end of the capacitor C25 is grounded to GND; the TX1P-L end, the TX1N-L end, the RX1P-L end and the RX1N-L end of the U12 are correspondingly connected with the TX1P-L end, the TX1N-L end, the RX1P-L end and the RX1N-L end of a chip U10 in the core processing circuit (320) respectively.
  10. 10. A vehicle retarder comprising a monitoring device as claimed in any one of claims 1 to 9.

Description

Monitoring device and vehicle speed reducer Technical Field The invention relates to the technical field of railway track traffic, in particular to a monitoring device of a vehicle speed reducer. Background Rail transit is an important form of transportation, diversion of freight rail transit relies on operation of humps, and vehicle reducers are one of the core devices of humps. The vehicle speed reducer is a device which clamps two sides of wheels of a railway vehicle by means of two braking rails and reduces the speed by means of friction, and a motor on the vehicle speed reducer is a device for providing power for the braking rails. With the rapid development of rail transit in China, the large-scale construction of humps is carried out, the freight transportation capacity and the freight volume are continuously improved, and the requirements on vehicle reducers are also higher and higher. In order to better monitor the braking state of the vehicle retarder, the braking pressure in the vehicle retarder and the hydraulic oil temperature in the hydraulic station with which the vehicle retarder is associated need to be monitored. However, there is no technology for reliably monitoring both the brake pressure and the oil temperature of a vehicle retarder on the vehicle retarder. Disclosure of Invention The invention aims at overcoming the technical defects existing in the prior art and provides a monitoring device and a vehicle speed reducer. To this end, the invention provides a monitoring device, which is applied to a vehicle speed reducer and comprises an oil pressure sensor, a temperature sensor and a collecting extension; the oil pressure sensor is used for collecting oil pressure in a hydraulic station originally matched with the vehicle speed reducer and then sending the oil pressure to the collecting extension; the temperature sensor is used for acquiring the oil temperature in the hydraulic station originally matched with the vehicle speed reducer and then sending the oil temperature to the acquisition extension; the collecting extension is respectively connected with the oil pressure sensor and the temperature sensor and is used for receiving the oil pressure data uploaded by the oil pressure sensor and the oil temperature data uploaded by the temperature sensor and then uploading the oil pressure data to an external computer; the acquisition extension comprises a plurality of external interfaces, a plurality of signal processing circuits, a power carrier processing circuit, a core processing circuit and a power supply circuit; the external interfaces are respectively and correspondingly connected with the signal processing circuits, the power carrier processing circuits and the core processing circuits; the plurality of signal processing circuits are connected with the core processing circuit; The core processing circuit is connected with the power carrier processing circuit; And the power supply circuit is respectively connected with the plurality of external interfaces, the plurality of signal processing circuits, the power carrier processing circuit and the core processing circuit. In addition, the invention also provides a vehicle speed reducer which comprises the monitoring device. Compared with the prior art, the technical scheme provided by the invention provides the monitoring device and the vehicle speed reducer, which are scientific in design, can safely and reliably monitor the braking state (particularly the braking pressure and the oil temperature of hydraulic oil) on the vehicle speed reducer, and have great practical significance in ensuring the operation safety of the vehicle speed reducer. In view of the fact that hydraulic oil at different temperatures has a certain influence on the braking ability of the retarder (the higher the temperature, the higher the fluidity of the hydraulic oil, the less viscous, and the lower the temperature, the lower the fluidity of the hydraulic oil, and the more viscous, and the braking effect of the typical vehicle retarder is poor). In addition, the braking pressure is high (the oil pressure of the hydraulic oil is high), and at this time, the braking effect corresponding to the normal vehicle retarder is good, whereas the braking pressure is low (the oil pressure of the hydraulic oil is low), and at this time, the braking effect of the normal vehicle retarder is poor. Therefore, with the device of the present invention, by focusing on the parameters of the brake pressure and the temperature at the same time, the brake state of the decelerator can be more deeply understood. The device provided by the invention can be reliably applied to vehicle speed reducer monitoring equipment in railway industry, and helps electric staff to better maintain and use the equipment. Drawings FIG. 1 is a block diagram showing a structure of a monitoring device according to the present invention; FIG. 2 is a schematic diagram of communication signals of an acquisiti