CN-121978384-A - Trigger system for source table and source table

CN121978384ACN 121978384 ACN121978384 ACN 121978384ACN-121978384-A

Abstract

The trigger system for the source list and the source list comprise a trigger logic processing module and a signal channel, wherein the signal channel comprises an ARM layer, a trigger layer and an execution layer, when the signal channel is in a ready state, the ARM layer is configured to be in an ARM layer normal mode, when a first expected trigger source signal is received, the first trigger signal is output, the trigger logic processing module is configured to respond to the first trigger signal to generate a state ready signal, when the trigger layer is configured to be in a trigger layer normal mode, the trigger layer is configured to respond to the state ready signal, when a second expected trigger source signal is received, the second trigger signal is output, the trigger logic processing module is configured to respond to the second trigger signal to generate an execution signal, and the execution layer is configured to respond to the execution signal to execute preset operation. By configuring the first expected trigger signal and the second expected trigger signal, the combination of different trigger source signals can be realized, the trigger source configuration is rich, the complex measurement and test environment requirements can be met, the use is simple, and the cost is reduced.

Inventors

Xie Bingtao
Mou Chi
WANG WENLONG

Assignees

深圳市鼎阳科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260401

Claims (10)

1. A trigger system for a source table is characterized by comprising a trigger logic processing module and at least one signal channel; The working state of the signal channel at least comprises a ready state, the signal channel comprises an ARM layer, a trigger layer and an execution layer, and the trigger logic processing module is connected with the ARM layer, the trigger layer and the execution layer, wherein the working mode of the ARM layer at least comprises an ARM layer normal mode; when the working state of the signal channel is the ready state: the ARM layer is configured to be capable of receiving a first trigger event when the ARM layer is in a working state and the working mode is the ARM layer normal mode, the first trigger event comprises a plurality of types of first trigger source signals, when the received first trigger event comprises a first expected trigger source signal, a first trigger signal is output to the trigger logic processing module, and the trigger logic processing module is configured to enable the trigger layer to enter the working state in response to the first trigger signal; The trigger layer is configured to be capable of receiving a second trigger event when the working state is in a normal mode of the trigger layer, the second trigger event comprises a plurality of types of second trigger source signals, when the second trigger event is received and comprises a signal conforming to a second expected trigger source, the second trigger event is output to the trigger logic processing module, and the trigger logic processing module is configured to generate an execution signal in response to the second trigger signal and output the execution signal to the execution layer; the execution layer is configured to perform a predetermined operation in response to the execution signal.
2. The trigger system for a source table of claim 1, wherein the first trigger event comprises a first internal trigger source signal, a first bus trigger source signal, a first local area network trigger source signal, and a first external trigger source signal, and/or wherein the second trigger event comprises a second internal trigger source signal, a second bus trigger source signal, a second local area network trigger source signal, and a second external trigger source signal.
3. The trigger system for a source table of claim 1 or 2, wherein the signal path comprises a hardware circuit connected to the trigger logic processing module, the ARM layer and the trigger layer sharing the hardware circuit; when the ARM layer is required to enter a working state, the trigger logic processing module is further configured to configure the hardware circuit as the ARM layer; When the trigger layer is required to enter a working state, the trigger logic processing module is further configured to configure the hardware circuit as the trigger layer.
4. The trigger system for a source table of claim 3, wherein the ARM layer operating mode further comprises an ARM layer bypass mode; when the ARM layer enters a working state and the working mode is the ARM layer bypass mode, the hardware circuit is configured to be switched to the trigger layer after entering the ARM layer; when the trigger layer enters a working state and the working mode is the trigger layer bypass mode, the trigger logic processing module generates the execution signal and outputs the execution signal to the execution layer.
5. The trigger system for a source table of claim 4, wherein the hardware circuit comprises a signal selection unit, a trigger counting unit, and a timing trigger signal generation unit, the trigger logic processing module being coupled to the signal selection unit, the trigger counting unit, and the internal signal generation unit; When the hardware circuit is configured as the ARM layer: The signal selection unit is configured to be capable of receiving the first trigger event when the working mode of the ARM is the ARM layer normal mode, and outputting the first trigger signal to the trigger logic processing module when the first expected trigger source signal is received; The trigger counting unit is configured to count up once when the first trigger event is received after the working mode of the ARM layer is determined to be the ARM layer normal mode, count up once after the working mode of the ARM layer is determined to be the ARM layer bypass mode, so as to generate a first count value, and output the first count value to the trigger logic processing module; the timing trigger signal generation unit is configured to generate a first internal timing trigger source signal in response to a first signal generation instruction; When the hardware circuit is configured as the trigger layer: The signal selection unit is configured to be capable of receiving the second trigger event when the working mode of the trigger layer is the normal mode of the trigger layer, and outputting the second trigger signal to the trigger logic processing module when the second expected trigger source signal is received; The trigger counting unit is configured to count up once when the second trigger event is received after the working mode of the trigger layer is determined to be the normal mode of the trigger layer, and count up once after the working mode of the trigger layer is determined to be the bypass mode of the trigger layer, so as to generate a second count value and output the second count value to the trigger logic processing module; the timing trigger signal generation unit is configured to generate a second internal timing trigger source signal in response to a second signal generation instruction; The trigger logic processing module is further configured to generate the first signal generation instruction when the first internal timing trigger source signal is included in the first trigger event, and is further configured to generate the second signal generation instruction when the second internal timing trigger source signal is included in the second trigger event.
6. The trigger system for a source meter of claim 5, wherein the operating state of the signal path further comprises an idle state; the trigger logic processing module is further configured to: After the execution layer executes the preset operation, judging whether the second count value reaches a second preset value, if the second count value reaches the second preset value, judging whether the first count value reaches a first preset value, if the first count value reaches the first preset value, switching the signal channel from the ready state to the idle state, and if the first count value does not reach the first preset value, configuring the hardware circuit into the ARM layer, wherein the ARM layer can receive the first trigger event when in the ARM layer normal mode, and output the first trigger signal when receiving the first expected trigger source signal; and if the second count value does not reach the second preset value, the hardware circuit is configured as the trigger layer, wherein the trigger layer can receive the second trigger event when in the normal mode of the trigger layer, and outputs the second trigger signal when receiving the second expected trigger source signal, and the trigger layer generates the execution signal and outputs the execution signal to the execution layer when in the bypass mode of the trigger wind.
7. The trigger system for a source table of claim 6, wherein the signal path switches from the idle state to the ready state in response to a user operation; when the signal channel is switched from the idle state to the ready state, the first count value is reset to a first initial value; When the hardware circuit is configured from the ARM layer switch to the trigger layer, the second count value is reset to a second initial value.
8. The trigger system for a source table according to claim 1 or 2, wherein the execution layer is further configured to output a pre-execution instruction signal before execution of the predetermined operation and to output a post-execution instruction signal after execution of the predetermined operation; the signal channel also comprises a state indication module, and the state indication module is connected with the trigger logic processing module; the trigger logic processing module is further configured to: When the ARM layer outputs enabling, a first state indication signal is output to the state indication module in response to the first trigger signal, so that the state indication module outputs an ARM layer action feedback signal when receiving an expected first state indication signal; when the output of the trigger layer is enabled, a second state indication signal is output to the state indication module in response to the second trigger signal, so that the state indication module outputs a trigger layer action feedback signal when receiving an expected second state indication signal; when the output of the execution layer is enabled, a third state indication signal is output to the state indication module in response to the pre-execution indication signal, so that the state indication module outputs a pre-execution layer action feedback signal when receiving an expected third state indication signal; And when the output of the execution layer is enabled, a fourth state indication signal is output to the state indication module in response to the post-execution indication signal, so that the state indication module outputs a feedback signal after the execution layer acts when receiving the expected fourth state indication signal.
9. The triggering system for a source meter according to claim 1 or 2, wherein the execution layer comprises an excitation output module and/or a measurement acquisition module; The excitation output module is configured to output an excitation signal to the device under test after receiving the execution signal; the measurement acquisition module is configured to acquire measurement data output by the device under test after receiving the execution signal.
10. A source table comprising a triggering system for a source table according to any one of claims 1-9.

Description

Trigger system for source table and source table Technical Field The invention relates to the technical field of measurement and test, in particular to a trigger system for a source table and the source table. Background The source measurement unit (Source Measure Unit, SMU), commonly called a source meter, is precision testing equipment integrating the functions of collecting voltage/current source and voltage/current measurement, and is widely applied to the fields of semiconductor device characteristic analysis, material electrical property test, integrated circuit test and the like. In an automated test system (ATE) or multi-channel parallel test scenario, a source meter is usually required to work together with a vector network analyzer, an oscilloscope, a probe station or other multiple source meters, so that the performance of a trigger system directly determines the synchronization accuracy and data consistency of the whole test system. In the prior art, the trigger system of the conventional source table can only set a single trigger source, that is, means that a user has no option when configuring software or hardware, and can only specify one trigger source. Only a single trigger source can be set, the configuration function is single, and the requirement of a complex measurement and test environment (automatic detection of industrial chips) cannot be met, so that a plurality of devices are required to cooperate to complete the test in the complex measurement and test environment, and the use is complex and the cost is high. Disclosure of Invention The invention mainly solves the technical problems that a trigger system can only be provided with a single trigger source, has a single configuration function and can not meet the requirement of a complex measurement and test environment, so that a plurality of devices are required to cooperate to complete the test in the complex measurement and test environment, and the use is complex and the cost is high. According to a first aspect, in one embodiment of the present application, there is provided a trigger system for a source table, including a trigger logic processing module and at least one signal path; The working state of the signal channel at least comprises a ready state, the signal channel comprises an ARM layer, a trigger layer and an execution layer, and the trigger logic processing module is connected with the ARM layer, the trigger layer and the execution layer, wherein the working mode of the ARM layer at least comprises an ARM layer normal mode; when the working state of the signal channel is the ready state: the ARM layer is configured to be capable of receiving a first trigger event when the ARM layer is in a working state and the working mode is the ARM layer normal mode, the first trigger event comprises a plurality of types of first trigger source signals, when the received first trigger event comprises a first expected trigger source signal, a first trigger signal is output to the trigger logic processing module, and the trigger logic processing module is configured to enable the trigger layer to enter the working state in response to the first trigger signal; The trigger layer is configured to be capable of receiving a second trigger event when the working state is in a normal mode of the trigger layer, the second trigger event comprises a plurality of types of second trigger source signals, when the second trigger event is received and comprises a signal conforming to a second expected trigger source, the second trigger event is output to the trigger logic processing module, and the trigger logic processing module is configured to generate an execution signal in response to the second trigger signal and output the execution signal to the execution layer; the execution layer is configured to perform a predetermined operation in response to the execution signal. In one embodiment, the first trigger event includes a first internal trigger source signal, a first bus trigger source signal, a first local area network trigger source signal, and a first external trigger source signal, and/or the second trigger event includes a second internal trigger source signal, a second bus trigger source signal, a second local area network trigger source signal, and a second external trigger source signal. In one embodiment, the signal channel comprises a hardware circuit, wherein the hardware circuit is connected with the trigger logic processing module, and the ARM layer and the trigger layer share the hardware circuit; when the ARM layer is required to enter a working state, the trigger logic processing module is further configured to configure the hardware circuit as the ARM layer; When the trigger layer is required to enter a working state, the trigger logic processing module is further configured to configure the hardware circuit as the trigger layer. In one embodiment, the working mode of the ARM layer further comprises an ARM layer bypass m