CN-121978402-A - Dicke type detector based on capacitive switching mechanism and detection method

CN121978402ACN 121978402 ACN121978402 ACN 121978402ACN-121978402-A

Abstract

A Dicke type detector and a detection method based on a capacitance switch mechanism belong to the fields of microwave measurement and radio frequency signal detection. A Dicke detector based on a capacitive switching mechanism comprises a main circuit and a control circuit. The main circuit comprises a signal switching and conditioning network, a sampling and holding network and a differential output network, and the control circuit mainly comprises a clock generator and a logic driving circuit. According to the invention, by constructing the two-way parallel capacitor sampling and holding network, the antenna signal and the reference load signal are respectively and completely stored and held, the problem of signal amplitude attenuation caused by duty ratio modulation of the traditional detector is solved, the response multiplication is realized, and the sensitivity of weak signal detection is improved. By implementing strict time sequence interlocking logic under clock control, the invention ensures that charge transfer is only carried out after sampling voltage is established stably and disconnected with an input end, can physically isolate and inhibit transient interference in the switching process of a radio frequency switch, and improves the accuracy and reliability of measurement.

Inventors

DANG HUA
ZHANG LEI
CHEN ZHIMING
YANG YIMING
GENG ZIHAN
LIU ZICHENG
LI XIAORAN

Assignees

北京理工大学

Dates

Publication Date: 20260505
Application Date: 20260126

Claims (10)

1. A Dicke type Detector based on a capacitance switching mechanism is characterized by comprising a main circuit and a control circuit, wherein the main circuit comprises a signal switching and conditioning network, a sampling and holding network and a differential output network, the signal switching and conditioning network comprises a radio frequency switch RF SPDT, a low noise amplifier LNA, a Detector and a baseband switch BB SPDT, and the sampling and holding network comprises a first intermediate sampling capacitor Second intermediate sampling capacitor A first holding capacitor A second holding capacitor A first charge transfer switch SPST1, a second charge transfer switch SPST2; the differential output network is mainly composed of a differential amplifier AMP; In the main circuit, a first input end of a radio frequency switch RF SPDT is connected with an antenna port and used for receiving a radio frequency signal to be detected, a second input end of the radio frequency switch RF SPDT is connected with a reference load port and used for receiving a reference thermal noise signal, a common output end of the radio frequency switch RF SPDT is connected with an input end of a low noise amplifier LNA, an output end of the low noise amplifier LNA is connected with an input end of a Detector, an output end of the Detector is connected with a common input end of a baseband switch BB SPDT, and a first output end of the baseband switch BB SPDT is connected with a first intermediate sampling capacitor A first output terminal of the baseband switch BB SPDT is also connected with an input terminal of the first charge transfer switch SPST1, a second output terminal of the baseband switch BB SPDT is connected with a second intermediate sampling capacitor A second output end of the baseband switch BB SPDT is also connected with an input end of the second charge transfer switch SPST2, a first intermediate sampling capacitor Second intermediate sampling capacitor The other end of the first charge transfer switch SPST1 is connected with the ground line, the output end of the first charge transfer switch SPST1 is connected with the first holding capacitor The output end of the first charge transfer switch SPST1 is also connected with the non-inverting input end of the differential amplifier AMP, the output end of the second charge transfer switch SPST2 is connected with the second holding capacitor The output end of the second charge transfer switch SPST2 is also connected with the inverting input end of the differential amplifier AMP, the first holding capacitor A second holding capacitor The output end of the differential amplifier AMP is used as the final signal output end of the Dicke type detector; The control circuit is mainly composed of a clock generator and a logic driving circuit.
2. The Dicke detector based on capacitive switching mechanism of claim 1, wherein the control circuit generates two complementary control signals which are not overlapped and have a predetermined dead time under the control of the clock module, and the driving circuit provides driving voltages for the radio frequency switch RF SPDT, the baseband switch BB SPDT, the first charge transfer switch SPST1 and the second charge transfer switch SPST2 in the main circuit after level conversion of the received logic signals, so that all the switching devices are controlled to operate in cooperation strictly according to a predetermined sequential logic, and isolation of a sampling process and a holding process in a time domain is ensured.
3. The Dicke type detector based on a capacitive switching mechanism as claimed in claim 2, wherein the sampling and holding network and the later-stage circuit are matched to enable a noise equivalent temperature difference NETD of the Dicke type detector under the driving of a 1MHz clock frequency to reach 0.25K, and a noise equivalent temperature difference under the driving of a 100kHz clock frequency to reach 0.824K.
4. The Dicke detector based on a capacitive switching mechanism as set forth in claim 2, wherein the impedance matching characteristics of the RF SPDT maintain an average input standing wave ratio VSWR within a passband below 1.67, the BB SPDT and the single pole single throw switch are configured to adapt to dual supply voltages of 1V and 1.8V to support an output voltage dynamic range of 0V to 1.8V, and the single channel operating power consumption is controlled at 41.8 mW.
5. The Dicke detector based on a capacitive switching mechanism as set forth in claim 2, wherein the differential amplifier AMP and its cascade circuit are configured to cover an equivalent input bright temperature range of 27.5K to 2188.4K and set a static output voltage of 0.374V to 0.4V in a normal temperature environment to realize linear amplification and readout of a wide temperature difference signal.
6. The Dicke detector based on capacitive switching mechanism as set forth in claim 2, wherein the Dicke detector has gain fluctuation controlled within + -1.03 dB in a passband in an operating frequency band of 88GHz to 98GHz, and the Dicke detector has a linear slope of 0.81 mV/K and a temperature stability of the linear slope maintained within + -0.051 mV/K.
7. The detection method of Dicke-type detector based on capacitive switching mechanism is realized based on Dicke-type detector based on capacitive switching mechanism as set forth in claim 1 or 2, and is characterized by comprising the following steps: when the clock is in high level state, the control circuit confirms the second intermediate sampling capacitor Disconnect from the front-end signal source and the first holding capacitor After the channel of the (B) switch is in an off state, the RF switch RF SPDT is driven to switch to the antenna channel and the baseband switch BB SPDT is driven to switch on the first output end, so that the antenna signal voltage is loaded to the first intermediate sampling capacitor The control circuit forcedly drives the first charge transfer switch SPST1 to keep an open state to block sampling transient noise, and drives the second charge transfer switch SPST2 to close to enable the second intermediate sampling capacitor to be connected with the second intermediate sampling capacitor The upper stored steady-state charge is transferred to the second holding capacitor ; Step two, when the clock is turned to a low level state, the control circuit confirms the first intermediate sampling capacitor Disconnect from the front-end signal source and a second holding capacitor After the path of the switch is in the off state, the RF switch RF SPDT is driven to switch to the reference load path and the baseband switch BB SPDT is driven to switch on the second output end, so that the load signal voltage is loaded to the second intermediate sampling capacitor The control circuit forcedly drives the second charge transfer switch SPST2 to keep an open state to isolate sampling fluctuation, and drives the first charge transfer switch SPST1 to be closed to drive the first intermediate sampling capacitor The upper stored steady state charge is transferred to the first holding capacitor ; Third, a first holding capacitor And a second holding capacitor Continuously maintaining the steady-state voltage of the antenna signal and the steady-state voltage of the load signal respectively, and continuously reading by a differential amplifier in a main circuit And (3) with The difference between the two ends of the antenna and the load signal is directly output to eliminate the difference between the antenna with the duty ratio modulation attenuation and the multiplied responsivity, so that the detection responsivity of the Dicke detector is improved.
8. The method for detecting a Dicke detector based on a capacitive switching mechanism as claimed in claim 7, wherein the step one is implemented by, When the clock is in a high level state, the control circuit executes sampling start logic in view of the second intermediate sampling capacitance at this time Must be in an isolated state from the front end and a first holding capacitor The control circuit drives the RF SPDT to switch to the antenna channel and drives the BB SPDT to switch on the first output terminal after confirming that the above conditions are satisfied, at this time, the signal link is conducted, the antenna signal voltage output by the detector Directly load to the first intermediate sampling capacitor The upper part of the upper part is provided with a plurality of grooves, The sampling mode of charge accumulation and voltage establishment is entered, the voltage at two ends of the sampling mode is changed along with the fluctuation of the front-end signal, and at the moment, a first middle sampling capacitor The instantaneous voltage on is expressed as: Wherein, the Is that The instantaneous voltage across the two terminals of the device, The control circuit executes global interlocking protection logic for the two channels in the process of inputting the radio frequency signal voltage to the antenna port, wherein the global interlocking protection logic comprises a first intermediate sampling capacitor An antenna signal voltage is being established but in view of a first intermediate sampling capacitance At this time, the front end signal source is directly conducted, and in order to meet the logic requirement that the sampling process never overlaps with the charge transfer process, the control circuit forcedly drives the first charge transfer switch SPST1 to keep the off state, and cuts off the first intermediate sampling capacitor through the interlocking action With the first holding capacitor of the subsequent stage The path between them, thus blocking the non-stationary ripple in the sampling setup process from the output stage, the interlock logic simultaneously acknowledges the second intermediate sampling capacitance at this time In an isolated state physically disconnected from the front-end signal source, for a first intermediate sampling capacitor Dynamic blocking and pairing of (a) Constitute complementary logic, clearly defining at the present moment only Steady-state conditions for data transfer are provided; the control circuit simultaneously performs output update interlock logic for the load channel when the clock is in a high state, detecting the second intermediate sampling capacitance At the moment, the control circuit drives the second charge transfer switch SPST2 to be closed immediately, and the second intermediate sampling capacitor is connected with the front-end signal source The upper stored steady state charge is rapidly transferred to the second holding capacitor through SPST2 Make the second holding capacitor The voltage at both ends is updated to be pure load signal voltage After the charge transfer is completed, a second holding capacitor The voltage state update of (2) is: Wherein, the To hold the capacitance Is set to a steady-state voltage of (1), For intermediate sampling capacitance The voltage maintained at the moment of disconnection, the output stage capacitance being ensured as the transfer process takes place after the preceding stage has been disconnected The access is only performed after the front-end voltage is completely stable, so that noise interference of the front-end circuit is avoided.
9. The method for detecting a Dicke detector based on a capacitive switching mechanism as claimed in claim 8, wherein the second implementation method is, When the clock is turned to a low level state, the control circuit executes load sampling start logic to confirm the first intermediate sampling capacitor Has been disconnected from the front-end signal source and at the same time confirms the second holding capacitance The control circuit drives the radio frequency switch RF SPDT to switch to the reference load channel and drives the baseband switch BB SPDT to switch on the second output end on the premise that the isolation condition is satisfied, and at the moment, the signal link is switched, and the load signal voltage output by the detector Directly loading to the second intermediate sampling capacitor On the second intermediate sampling capacitor A sampling mode of charge accumulation and voltage establishment is entered, the voltage of two ends of the sampling mode changes along with the establishment of a load thermal noise signal, a second intermediate sampling capacitor is arranged at the moment The instantaneous voltage on is expressed as: Wherein, the Is that The instantaneous voltage across the two terminals of the device, The control circuit executes global interlock protection logic for the dual channel during this process taking into account the noise signal voltage input to the reference load port In the dynamic sampling phase directly connected with the detector, the voltage is not stable and contains switching noise, and in order to ensure that the condition that sampling and transferring are not overlapped is continuously met, the control circuit forcedly drives the second charge transfer switch SPST2 to keep an off state, and the second charge transfer switch SPST2 is cut off through interlocking action And a second storage capacitor at the subsequent stage The passage between the first and second capacitors ensures the second holding capacitance The voltage on the capacitor is not interfered by the current load sampling establishment process, the stability of the reference signal is maintained, and the interlocking logic simultaneously confirms the first intermediate sampling capacitor at the moment Has been in an isolated state from the front-end signal source Dynamic blocking and pairing of (a) Is again complementary, clearly defined at the present moment only Steady-state conditions for data transfer are provided; When the clock is turned to a low state, the control circuit simultaneously performs an output update interlock logic for the antenna channel using the first intermediate sampling capacitance at this time After confirming that the time sequence requirements of 'first stable and then transfer' in full-period signal processing are met, the control circuit drives the first charge transfer switch SPST1 to be closed, and at the moment, the first intermediate sampling capacitor The upper stored steady state charge is transferred to the first holding capacitor through SPST1 Make the first holding capacitor The voltage at both ends is updated to the antenna signal voltage After the charge transfer is completed, a first holding capacitor The voltage state update of (2) is: Wherein, the Is the first holding capacitance Is set to a steady-state voltage of (1), For the first intermediate sampling capacitor The interlock logic ensures the first holding capacitance of the output stage Only at The data updating is carried out after the signal is completely established at the steady state and separated from the input end, so that the high-precision signal maintenance is realized.
10. The method for detecting a Dicke detector based on a capacitive switching mechanism as claimed in claim 9, wherein the third implementation method is that, Through the alternate cyclic operation of the first step and the second step, the Dicke type detector strictly executes time sequence interlocking in each complete clock period, wherein sampling is only carried out in a non-transfer period, transfer is only carried out in a steady-state period after a signal source is disconnected, and under the mechanism, the first holding capacitor is used for the first clock period And a second holding capacitor Are in a continuously effective voltage-holding state, in which The latest antenna signal voltage is always maintained, Always keeping the latest load signal voltage, and continuously reading the differential amplifier in the main circuit And (3) with The potential difference between the two ends and the output voltage Expressed as: Wherein, the The gain of the differential amplifier, the difference value between the antenna signal and the load signal can be completely reproduced by the output signal, the full-period signal utilization is realized, and the amplitude of the output signal is kept to be the full amplitude value of the signal difference value in the full clock period without duty cycle average processing because the output signal is derived from the direct-current steady-state voltage of the holding capacitor purified by the interlocking logic, thereby realizing the multiplication of the responsivity of the Dicke detector.

Description

Dicke type detector based on capacitive switching mechanism and detection method Technical Field The invention belongs to the technical field of microwave measurement and radio frequency signal detection, and relates to a Dike Dicke detector circuit based on a capacitive switch mechanism and a detection method thereof. Background With the rapid development of microwave remote sensing, radio astronomy and passive imaging technologies, the requirements on weak signal detection sensitivity and stability are increasingly increased. In these applications, the receiver is not only challenged by the requirement of extremely low signal-to-noise ratio, but also the gain fluctuation of the system itself and the flicker noise (1/f noise) inherent in the low frequency electronic device can seriously affect the identification and detection of the target signal to be detected. To address this problem, the dick (Dicke) radiometer regime is widely used. The conventional Dike detector uses a radio frequency switch to periodically modulate between an antenna signal to be detected and a reference load signal by introducing a constant temperature reference load, and moves a direct current or low frequency signal to be detected to a switching frequency, and obtains the difference between the antenna temperature and the load temperature after detection, synchronous demodulation and integration processing. The method effectively eliminates the gain fluctuation and background thermal noise of the receiver and avoids the low-frequency noise area. However, conventional disco detector designs suffer from non-negligible inherent drawbacks. First is the problem of halving the responsivity. Since the rf switch is typically switched between the antenna and the load at a 50% duty cycle, the subsequent synchronous detection circuit actually slices the signal, resulting in a final integrated output with a voltage amplitude that is only half the difference between the antenna signal and the load signal (i.e.). This means that the system has half the time in the non-full signal receiving state, directly limiting the sensitivity and responsiveness of the detector. And secondly, the problem of switching transient interference. At the instant of high-speed switching of the rf switch, parasitic capacitance and non-ideal switching characteristics can create charge injection effects or voltage spikes. If these transient responses enter the subsequent high sensitivity detection circuit directly without isolation, additional noise floor and measurement errors are introduced, and the influence of this transient disturbance is particularly serious, especially in high frequency broadband applications. Existing improvements, while attempting to compensate for the lack of responsiveness by increasing the pre-amplification gain or employing digital correlation techniques, tend to be at the expense of system complexity and power consumption, and it is difficult to fundamentally eliminate transient disturbances caused by switching. Therefore, a new detector circuit topology and control method that can simultaneously achieve full-period signal utilization, responsivity multiplication, and effective suppression of switching transient disturbances are needed. Disclosure of Invention The invention aims to provide a Dicke-type detector based on a capacitive switching mechanism, which is a detector circuit with a topological structure, and can respectively and completely store and hold an antenna signal and a reference load signal by constructing a two-way parallel capacitive sampling and holding network, so that the problem of signal amplitude attenuation caused by duty ratio modulation of a traditional Dicke-type detector is solved, the multiplication of responsiveness is realized, and the sensitivity of weak signal detection is improved. On the basis of the Dicke-type detector based on the capacitive switching mechanism, the second purpose of the invention is to provide a Dicke-type detector based on the capacitive switching mechanism, and by implementing strict time sequence interlocking logic under clock control, charge transfer is ensured to be carried out only after sampling voltage is established stably and disconnected from an input end, transient interference in the switching process of a radio frequency switch can be physically isolated and suppressed, and the accuracy and reliability of measurement are improved. The invention aims at realizing the following technical scheme: the invention discloses a Dicke detector based on a capacitive switching mechanism, which comprises a main circuit and a control circuit. The main circuit comprises a signal switching and conditioning network, a sample and hold network and a differential output network. The signal switching and conditioning network includes a radio frequency switch RF SPDT, a low noise amplifier LNA, a Detector, and a baseband switch BB SPDT. The sample-and-hold network comprises a first intermedia