CN-121978498-A - Method for determining effective channel length of device

CN121978498ACN 121978498 ACN121978498 ACN 121978498ACN-121978498-A

Abstract

The application provides a method for determining the effective channel length of a device, which is based on the lengths of a plurality of grid electrodes ) Capacitance-voltage correspondence corresponding to each other, and obtaining the charge concentration of the inversion layer corresponding to each of the gate lengths by integration ). By the ratio of the inversion layer charge concentration and the grid channel capacitance ) And inversion layer charge concentration [ ] ) Linear fitting vs ) Determining the capacitance of the gate oxide layer in unit area corresponding to the lengths of the multiple gates based on the fitting slope ). Because the capacitor has direct influence on the channel potential distribution, the influence of carrier transport nonideal factors is relatively small, and accurate implementation is realized Extracting. On the basis, the effective channel length of the target device can be determined ) Thus will be advanced Combining extraction technique with physical model of effective channel length extraction to determine accuracy The accurate effective channel length is calculated according to the method, so that reliable and accurate effective channel length characterization is realized.

Inventors

YAN YU
YUAN ZHENGWU
Dou Cunhua
CHEN YONGXIN
XU YONG
LI BINHONG
Solin Koristonov

Assignees

广东省大湾区集成电路与系统应用研究院

Dates

Publication Date: 20260505
Application Date: 20260331

Claims (10)

1. A method of determining an effective channel length of a device, the method comprising: Carrying out grid channel capacitance test under different grid voltages on the device to be tested with different grid lengths to obtain capacitance-voltage corresponding relations corresponding to the multiple grid lengths respectively; Performing integral operation based on gate voltage on the gate channel capacitance based on the capacitance-voltage correspondence relationship to obtain inversion layer charge concentrations corresponding to the gate lengths respectively; The ratio of the inversion layer charge concentration to the grid channel capacitance and the inversion layer charge concentration are subjected to linear fitting, and the grid oxide layer capacitance of a unit area corresponding to each of the plurality of grid lengths is determined based on fitting slopes; Respectively calculating to obtain actual inversion layer capacitances corresponding to the gate lengths according to the gate lengths, the channel width of the device to be tested and the gate oxide layer capacitance of the unit area; Determining an amount of error between the gate length and the effective channel length at the plurality of gate lengths based on the fitting intercept by performing a linear fit on the actual inversion layer capacitance and the plurality of gate lengths; For a target device in the devices to be tested, the target device has a first length in the gate lengths, and the effective channel length of the target device is determined according to the first length and the error amount corresponding to the first length.
2. The method of claim 1, wherein the calculating the actual inversion layer capacitances corresponding to the gate lengths respectively according to the gate lengths, the channel widths of the device under test, and the gate oxide capacitance per unit area comprises: And taking the product of the second length, the channel width of the device to be tested and the gate oxide layer capacitance of the unit area corresponding to the second length as the actual inversion layer capacitance corresponding to the second length aiming at the second length in the plurality of gate lengths.
3. The method of claim 1, wherein the determining the gate oxide capacitance per unit area for each of the plurality of gate lengths based on the fitting slope by linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance, and the inversion layer charge concentration, comprises: and performing linear fitting on the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, and taking the inverse of the fitting slope as the gate oxide layer capacitance of the unit area corresponding to the gate lengths respectively.
4. The method of claim 1, wherein the device under test comprises a plurality of first devices, the gate lengths of the first devices are each a third length of the plurality of gate lengths, and the capacitance-voltage correspondence under the plurality of gate lengths is that of a single device under the plurality of gate lengths; The step of testing the capacitance of the gate channel under different gate voltages for the device to be tested with different gate lengths to obtain the capacitance-voltage correspondence corresponding to the gate lengths respectively comprises the following steps: carrying out grid channel capacitance test on the plurality of first devices connected in parallel under different grid voltages to obtain a total capacitance voltage corresponding relation under the third length; And determining the capacitance voltage corresponding relation of the single device under the third length based on the number of the first devices and the total capacitance voltage corresponding relation.
5. The method of claim 4, wherein the gates of the plurality of first devices are connected together, the sources of the plurality of first devices are connected together, and the drains of the plurality of first devices are connected together in parallel.
6. The method of claim 4, wherein the third length is less than or equal to 200nm.
7. The method of claim 5, wherein the third length is less than or equal to 100nm.
8. The method of any of claims 1-7, wherein the device under test comprises a substrate, a buried oxide layer and a channel layer sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source and a drain on opposite sides of the channel layer, respectively.
9. The method of claim 8, wherein the buried oxide layer has a thickness in the range of 20-25nm, and/or the channel layer has a thickness of less than or equal to 12nm, and/or the channel layer has a doping concentration in the range of 1 x 10 15 ~1×10 16 cm - .
10. The method of any one of claims 1-7, wherein the gate voltage is in a range of-0.2 v to 1v.

Description

Method for determining effective channel length of device Technical Field The invention relates to the field of semiconductors, in particular to a method for determining the effective channel length of a device. Background As integrated circuit fabrication processes continue to evolve, device dimensions continue to shrink, new structures such as Fully Depleted Silicon On Insulator (FDSOI) have received much attention due to their excellent segment channel effect suppression capability and low power consumption characteristics. In these advanced devices, low doping and even near intrinsic channel regions are commonly employed in order to further improve performance and reduce power consumption, while the equivalent oxide thickness (Equivalent Oxide Thickness, EOT) of the gate oxide has also been reduced to ultra-thin dimensions. This feature presents new challenges for accurate extraction of device critical parameters, resulting in conventional effective channel lengths (EFFECTIVE CHANNEL LENGTH,) And (3) larger errors exist in the determination of the process, so that the requirements of process monitoring and device modeling are difficult to meet increasingly. Disclosure of Invention In view of the above, the application aims to provide a method for determining the effective channel length of a device, which realizes reliable and accurate effective channel length characterization. The embodiment of the application provides a method for determining the effective channel length of a device, which comprises the following steps: Carrying out grid channel capacitance test under different grid voltages on the device to be tested with different grid lengths to obtain capacitance-voltage corresponding relations corresponding to the multiple grid lengths respectively; Performing integral operation based on gate voltage on the gate channel capacitance based on the capacitance-voltage correspondence relationship to obtain inversion layer charge concentrations corresponding to the gate lengths respectively; The ratio of the inversion layer charge concentration to the grid channel capacitance and the inversion layer charge concentration are subjected to linear fitting, and the grid oxide layer capacitance of a unit area corresponding to each of the plurality of grid lengths is determined based on fitting slopes; Respectively calculating to obtain actual inversion layer capacitances corresponding to the gate lengths according to the gate lengths, the channel width of the device to be tested and the gate oxide layer capacitance of the unit area; Determining an amount of error between the gate length and the effective channel length at the plurality of gate lengths based on the fitting intercept by performing a linear fit on the actual inversion layer capacitance and the plurality of gate lengths; For a target device in the devices to be tested, the target device has a first length in the gate lengths, and the effective channel length of the target device is determined according to the first length and the error amount corresponding to the first length. As a possible implementation manner, the calculating, according to the gate lengths, the channel widths of the device under test, and the gate oxide capacitance per unit area, the actual inversion layer capacitances corresponding to the gate lengths respectively includes: And taking the product of the second length, the channel width of the device to be tested and the gate oxide layer capacitance of the unit area corresponding to the second length as the actual inversion layer capacitance corresponding to the second length aiming at the second length in the plurality of gate lengths. As a possible implementation manner, the determining the gate oxide capacitance per unit area corresponding to the gate lengths respectively based on the fitting slope by performing linear fitting on the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration includes: and performing linear fitting on the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, and taking the inverse of the fitting slope as the gate oxide layer capacitance of the unit area corresponding to the gate lengths respectively. As one possible implementation manner, the device under test includes a plurality of first devices, the gate lengths of the first devices are all third lengths in the plurality of gate lengths, and the capacitance-voltage correspondence relationship under the plurality of gate lengths is that of a single device under the plurality of gate lengths; The step of testing the capacitance of the gate channel under different gate voltages for the device to be tested with different gate lengths to obtain the capacitance-voltage correspondence corresponding to the gate lengths respectively comprises the following steps: carrying out grid channel capacitance test o