CN-121978501-A - Chip, test method thereof, computer equipment and storage medium

CN121978501ACN 121978501 ACN121978501 ACN 121978501ACN-121978501-A

Abstract

The embodiment of the application provides a chip, a testing method thereof, computer equipment and a storage medium, wherein the chip comprises a mode switching module, an input decompressing module and an output compressing module, the output compressing module is provided with a frequency tripler clock and is used for outputting a response signal output by a scanning chain in the chip in a time division multiplexing mode in a plurality of compressed clock cycles to a pin for testing the final scanning chain under the final scanning chain testing mode, the mode switching module is provided with a control pin, a multiplexer and a multiplexed wafer scanning chain testing pin, the multiplexer is driven to switch the testing mode by a control signal output by the control pin, and the input decompressing module comprises a multistage register and a combination logic. The application can improve the efficiency and accuracy of the test.

Inventors

WANG XIAOJIN
QIU JIANGLIN
Liu Gebo
LAI NAI

Assignees

珠海妙存科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251202

Claims (10)

1. A chip comprising a mode switching module, an input decompression module, and an output compression module, comprising: the output compression module is configured with a triple frequency clock and is used for outputting the response signals output by the scanning chain in the chip in a time division multiplexing mode in a plurality of compression clock periods to the pins of the compressed final scanning chain test in a final scanning chain test mode; the mode switching module is configured with a control pin, a multiplexer and a multiplexed wafer scanning chain test pin, and the control signal output by the control pin drives the multiplexer to switch the test mode; the input decompression module includes a multi-stage register and combinational logic.
2. The chip of claim 1, wherein the test modes include a wafer scan chain test mode and a final scan chain test mode, the multiplexed wafer scan chain test pins serving as input pins and output pins in the final scan chain test mode.
3. The chip of claim 1, wherein the input decompression module is configured to receive, in the final scan chain test mode, multi-beat compressed data input in the final scan chain test mode according to a preset compression specification, latch and splice the multi-level register in cycles, restore a test vector in the wafer scan chain test mode, and input the test vector to the internal scan chain of the chip.
4. The chip of claim 2, wherein in the wafer scan chain test mode, the mode switching module comprises: The input signal and the output signal of the scanning chain in the wafer scanning chain test mode are directly connected with the internal scanning chain of the chip through the multiplexer, the input decompression module and the output compression module are in an idle state.
5. The chip testing method is characterized by being applied to a chip, wherein the chip comprises a mode switching module, an input decompressing module and an output compressing module, and comprises the following steps: acquiring the compression specification of the input decompression module and the time division multiplexing rule of the output compression module; Converting a scan chain test vector of a wafer scan chain test mode into a scan chain test vector of a final scan chain test mode according to the compression specification and the time division multiplexing rule, wherein the scan chain test vector of the final scan chain test mode comprises a compressed final scan chain test input vector and a corresponding expected final scan chain test output response; Loading a scan chain test vector of the final scan chain test mode to a chip through an ATE machine table, setting a control pin as a final scan chain test mode level, reducing the test vector into a test vector of the original wafer scan chain test mode through the input decompression module, inputting the test vector into an internal scan chain of the chip, and outputting a final scan chain test response signal through the output compression module; Comparing the final scan chain test response signal with the expected final scan chain test output response signal to obtain a comparison result; and obtaining a chip logic fault judging result according to the comparison result.
6. The method as recited in claim 5, further comprising: and outputting target total digital wafer scan chain test response signals output by the internal scan chain of the chip in sequence according to the preset period of the frequency tripling clock, wherein each preset period outputs target digital response data.
7. The method of claim 6, wherein the restoring, by the input decompression module, to the test vector for the raw wafer scan chain test pattern comprises: Receiving first beat of compressed data through the input decompression module and latching the first beat of compressed data to a low-target digital register in a first preset period of the frequency tripled clock; receiving second beat of compressed data through the input decompression module and latching the second beat of compressed data to a high-target digital register in a second preset period of the frequency tripling clock; and in a third preset period of the frequency tripling clock, receiving third beat of compressed data through the input decompression module, splicing the third beat of compressed data with the data latched by the low-target digital register and the high-target digital register, and restoring the third beat of compressed data into a test vector of the wafer scan chain test mode of the target total digital.
8. The method of claim 5, wherein the obtaining a chip logic fault determination result according to the comparison result comprises: when the comparison result represents that the final scan chain test response signal is completely consistent with the expected final scan chain test output response, a chip logic fault judgment result is that the chip has no logic fault; and when the comparison result represents that the final scan chain test response signal is inconsistent with the expected final scan chain test output response, obtaining a chip logic fault judgment result, namely that the chip has a logic fault and locating a fault position.
9. A computer device, comprising: at least one memory; At least one processor; At least one computer program; the at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method of any one of claims 5 to 8.
10. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for causing a computer to execute the method according to any one of claims 5 to 8.

Description

Chip, test method thereof, computer equipment and storage medium Technical Field The present application relates to the field of chip technologies, and in particular, to a chip, a testing method thereof, a computer device, and a storage medium. Background In the related art, the number of PINs after chip packaging is limited, and the conventional design improves the compression ratio by integrating a high compression ratio Compressor (Compressor) and decompressor (Decompressor) module inside the chip. The high compression ratio requires more complex compression and decompression logic, resulting in reduced fault diagnosis accuracy and loss of coverage. Disclosure of Invention The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a chip, a testing method thereof, computer equipment and a storage medium, and aims to improve the testing efficiency and accuracy. In a first aspect, an embodiment of the present application provides a chip, where the chip includes a mode switching module, an input decompression module, and an output compression module, and includes: the output compression module is configured with a triple frequency clock and is used for outputting the response signals output by the scanning chain in the chip in a time division multiplexing mode in a plurality of compression clock periods to the pins of the compressed final scanning chain test in a final scanning chain test mode; the mode switching module is configured with a control pin, a multiplexer and a multiplexed wafer scanning chain test pin, and the control signal output by the control pin drives the multiplexer to switch the test mode; the input decompression module includes a multi-stage register and combinational logic. According to some embodiments of the application, the test modes include a wafer scan chain test mode and a final scan chain test mode, the multiplexed wafer scan chain test pins serving as input pins and output pins in the final scan chain test mode. According to some embodiments of the present application, the input decompression module is configured to receive, in the final scan chain test mode, multiple beats of compressed data input in the final scan chain test mode according to a preset compression specification, latch and splice the multiple beats of compressed data periodically by the multi-stage register, restore the compressed data to a test vector in the wafer scan chain test mode, and input the test vector to the internal scan chain of the chip. According to some embodiments of the application, in the wafer scan chain test mode, the mode switching module includes: The input signal and the output signal of the scanning chain in the wafer scanning chain test mode are directly connected with the internal scanning chain of the chip through the multiplexer, the input decompression module and the output compression module are in an idle state. In a second aspect, an embodiment of the present application provides a method for testing a chip, where the chip includes a mode switching module, an input decompression module, and an output compression module, and the method includes: acquiring the compression specification of the input decompression module and the time division multiplexing rule of the output compression module; Converting a scan chain test vector of a wafer scan chain test mode into a scan chain test vector of a final scan chain test mode according to the compression specification and the time division multiplexing rule, wherein the scan chain test vector of the final scan chain test mode comprises a compressed final scan chain test input vector and a corresponding expected final scan chain test output response; Loading a scan chain test vector of the final scan chain test mode to a chip through an ATE machine table, setting a control pin as a final scan chain test mode level, reducing the test vector into a test vector of the original wafer scan chain test mode through the input decompression module, inputting the test vector into an internal scan chain of the chip, and outputting a final scan chain test response signal through the output compression module; Comparing the final scan chain test response signal with the expected final scan chain test output response signal to obtain a comparison result; and obtaining a chip logic fault judging result according to the comparison result. According to some embodiments of the application, further comprising: and outputting target total digital wafer scan chain test response signals output by the internal scan chain of the chip in sequence according to the preset period of the frequency tripling clock, wherein each preset period outputs target digital response data. According to some embodiments of the application, the restoring, by the input decompression module, the test vector of the original wafer scan chain test mode includes: Receiving first beat of compressed data thr