CN-121978502-A - Time interval measuring method, device, semiconductor test equipment and storage medium

CN121978502ACN 121978502 ACN121978502 ACN 121978502ACN-121978502-A

Abstract

The application is applicable to the technical field of semiconductor chip testing, and provides a time interval measuring method, a device, semiconductor testing equipment and a storage medium, wherein the method comprises the steps of acquiring a measured start signal and a measured stop signal; the method comprises the steps of counting the number of clock cycles spanned between a start signal and a stop signal through a system clock to obtain integer time, controlling the start signal to be transmitted through a carry delay chain, latching the output of the carry delay chain at the trigger edge of the system clock, counting the number of delay units at a preset level in a latching result, accessing a delay lookup table, searching corresponding path time according to the number of delay units and the delay lookup table to obtain decimal time, wherein the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain, and determining a time interval measurement result between the start signal and the stop signal according to the integer time and the decimal time. The scheme can improve the accuracy and stability of time interval measurement.

Inventors

WANG HAO
DAI MENG
CHEN XI
MA XUEZHEN

Assignees

深圳市辰卓科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251229

Claims (10)

1. The time interval measuring method is characterized by being applied to semiconductor test equipment, wherein the semiconductor test equipment at least comprises a programmable logic unit, a carry delay chain formed by cascading a plurality of carry logic units is arranged in the programmable logic unit, and the method comprises the following steps of: acquiring a measured start signal and a measured stop signal; Counting the number of clock cycles spanned between the start signal and the stop signal by a system clock to obtain integer time; controlling the starting signal to be transmitted through the carry delay chain, latching the output of the carry delay chain at the trigger edge of the system clock, and counting the number of delay units at a preset level in a latching result; Accessing a delay lookup table, and searching corresponding path time according to the number of delay units and the delay lookup table to obtain decimal time, wherein the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain and comprises a mapping relation between the number of delay units and the corresponding path time; and determining a time interval measurement result between the start signal and the stop signal according to the integer time and the decimal time.
2. The method of claim 1, wherein latching the output of the carry delay chain at the triggering edge of the system clock and counting the number of delay cells at a preset level in the latched result comprises: After the initial signal enters the carry delay chain, controlling the output of all levels of taps of the carry delay chain to form a level state; Synchronously latching the output of each level of tap by adopting a trigger array at the triggering edge of the system clock to obtain a latching code; and counting bits in a preset level in the latch code to obtain the number of the delay units.
3. The method of claim 2, further comprising, prior to the number of delay cells in the statistical latch result being at a preset level: Judging whether the latch code is a thermometer code with bubbles; When the latch code is a thermometer code with bubbles, ascending sort is carried out on path time corresponding to each tap of the carry delay chain, and a delay sorting result is obtained; rearranging and mapping the latch output of the trigger array based on the delay sequencing result; counting the rearranged and mapped latch codes to obtain the number of the delay units.
4. The method of claim 1, wherein accessing the delay lookup table, looking up corresponding path times based on the number of delay elements and the delay lookup table, to obtain fractional times, comprises: Taking the number of the delay units as an index value; reading path time corresponding to the index value in the delay lookup table; and outputting the read path time as the decimal time.
5. The method of claim 1, wherein the delay look-up table is predetermined based on a timing analysis result of the carry delay chain, comprising: acquiring data path information in a time sequence report of a programmable logic unit development tool; Extracting path delay from the initial signal to tap outputs of each stage and to a latch register; carrying out differential operation on path delays output by adjacent taps to obtain incremental delays of each stage; and accumulating the increment delays of all levels to generate a mapping relation between the number of delay units and path time, thereby forming the delay lookup table.
6. The method of claim 1, wherein the delay look-up table is predetermined based on a timing analysis result of the carry delay chain, comprising: acquiring the integral path delay of each carry logic unit in the carry delay chain; And taking the whole path delay of each carry logic unit as the delay amount of one delay unit, and constructing a delay lookup table based on the delay amount, so that the delay lookup table comprises the mapping relation between the number of delay units and the corresponding path time.
7. The method of any of claims 1 to 6, wherein counting the number of clock cycles spanned between the start signal and the stop signal by a system clock results in an integer time, comprising: starting a counter and starting counting a system clock when the start signal is detected; stopping the counter upon detection of the stop signal; and multiplying the count value of the counter by the system clock period to obtain the integer time.
8. The time interval measuring device is characterized by being arranged in semiconductor test equipment, wherein the semiconductor test equipment at least comprises a programmable logic unit, a carry delay chain formed by cascading a plurality of carry logic units is arranged in the programmable logic unit, and the device comprises: The signal acquisition module is used for acquiring a measured start signal and a measured stop signal; The integer time determining module is used for counting the clock cycle number spanned between the starting signal and the stopping signal through a system clock to obtain integer time; The delay quantity determining module is used for controlling the transmission of the initial signal through the carry delay chain, latching the output of the carry delay chain at the trigger edge of the system clock, and counting the quantity of delay units at a preset level in a latching result; The decimal time determining module is used for accessing a delay lookup table, searching corresponding path time according to the number of delay units and the delay lookup table to obtain decimal time, wherein the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain and comprises a mapping relation between the number of delay units and the corresponding path time; and the measurement result determining module is used for determining a time interval measurement result between the starting signal and the stopping signal according to the integer time and the decimal time.
9. A semiconductor test apparatus comprising a memory, a processor, a programmable logic unit, and a computer program stored in the memory and operable on the programmable logic unit; The programmable logic unit is provided with a carry delay chain formed by cascading a plurality of carry logic units and a delay lookup table, wherein the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain and comprises a mapping relation between the number of delay units and corresponding path time; The programmable logic unit, when executing the computer program, is adapted to implement the method of any one of claims 1 to 7.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 7.

Description

Time interval measuring method, device, semiconductor test equipment and storage medium Technical Field The present application relates to the field of semiconductor chip testing technology, and in particular, to a time interval measurement method and apparatus, a semiconductor testing device, and a storage medium. Background In semiconductor test equipment, it is often necessary to measure with high accuracy the time interval between the start signal and the stop signal of the signal under test. The existing time-to-digital converter is realized by combining system clock counting with subdivision delay interpolation, wherein subdivision delay is usually completed by depending on an internal delay structure of a programmable logic device. Because the internal delay of the device is influenced by the process, the temperature, the voltage and the layout wiring, the linearity and the consistency of the subdivision delay are difficult to ensure, and the nonlinear error of the measurement result is easy to occur. On the other hand, calibration and data processing are often needed to obtain higher precision, so that the complexity and resource cost of a test flow are increased, and the efficiency and stability under a high throughput test scene are not improved. Disclosure of Invention In view of this, the embodiments of the present application provide a time interval measurement method, apparatus, semiconductor test device, and storage medium, which can improve accuracy and stability of time interval measurement without increasing the burden of complex calibration and data processing, and reduce the influence of nonlinear errors on test results. A first aspect of the embodiment of the present application provides a time interval measurement method applied to a semiconductor test device, wherein the semiconductor test device at least comprises a programmable logic unit, the programmable logic unit is provided with a carry delay chain formed by cascade connection of a plurality of carry logic units, and the method comprises: acquiring a measured start signal and a measured stop signal; Counting the number of clock cycles spanned between the start signal and the stop signal by a system clock to obtain integer time; controlling the starting signal to be transmitted through the carry delay chain, latching the output of the carry delay chain at the trigger edge of the system clock, and counting the number of delay units at a preset level in a latching result; Accessing a delay lookup table, and searching corresponding path time according to the number of delay units and the delay lookup table to obtain decimal time, wherein the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain and comprises a mapping relation between the number of delay units and the corresponding path time; and determining a time interval measurement result between the start signal and the stop signal according to the integer time and the decimal time. In the embodiment of the application, firstly, a measured start signal and a measured stop signal are obtained, and the number of clock periods spanned between the start signal and the stop signal is counted through a system clock to obtain integer time, so that a main body part of a time interval can be obtained by taking the system clock period as a quantization unit, the measurement range is ensured, on the basis, the start signal is further controlled to be transmitted through a carry delay chain, the output of the carry delay chain is latched and counted at the triggering edge of the system clock, the number of delay units at a preset level in a latching result is counted, so that the propagation position of the start signal in one clock period is converted into a computable fine component, then, the number of delay units is mapped into corresponding path time to obtain fractional time by accessing a delay lookup table predetermined based on the timing analysis result of the carry delay chain, so that a time part which cannot be quantized by a counter can be effectively represented, and finally, the time interval measurement result between the start signal and the stop signal is determined according to the integer time and the fractional time. According to the scheme, the combination measurement of the integer time and the decimal time is realized by utilizing the carry delay chain in the programmable logic unit of the semiconductor test equipment and combining the predetermined delay lookup table, so that the accuracy and the stability of time interval measurement can be improved on the premise of not increasing the burden of complex calibration and data processing, and the influence of nonlinear errors on the test result can be reduced. In one possible implementation manner, the latching the output of the carry delay chain at the trigger edge of the system clock and counting the number of delay units in the latching result at a preset level inc