CN-121978505-A - Automatic testing system based on upper computer backboard

CN121978505ACN 121978505 ACN121978505 ACN 121978505ACN-121978505-A

Abstract

The invention relates to the field of automatic testing of back boards, in particular to an automatic testing system based on a back board of an upper computer, which comprises an upper computer module, a main MCU, a control module and a control module, wherein the upper computer module is used for customizing test items, arranging test sequences, setting test parameters and judging rules, sequentially issuing configuration information to the main MCU and providing a graphical test configuration interface; and the main MCU module is used for testing and executing the core scheduler and running real-time operating system (RTOS) software. Through the software definition test, the firmware function curing mode is thoroughly changed through the upper computer custom test flow, so that the test tool can be quickly adapted to new products and new test demands, the flexibility and the universality are greatly improved, the one-time development and multiple adaptation are realized, meanwhile, the type of the test backboard can be subjected to the upper computer custom test project, a test instruction set is generated and sequentially issued to the main control module, and the main control module dynamically dispatches and executes operation instructions and feeds back data.

Inventors

LAI LIUQI
YANG HAO
ZHANG XIN
LI QIANG
CHEN LONGFEI

Assignees

重庆云铭科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260203

Claims (10)

1. An automatic testing system based on an upper computer backboard is characterized by comprising the following components: The upper computer module is used for customizing test items, arranging test sequences, setting test parameters and judging rules, sequentially issuing configuration information to the main MCU, and providing a graphical test configuration interface; the main MCU module is used for testing and executing a core scheduler and running real-time operating system (RTOS) software; The test load module is used for connecting the two buses with the main MCU and the test backboard MCU, and is used for switching in various modes such as open circuit, short circuit, fixed resistance, simulated detonator load and the like according to the instruction of the upper computer through the load switching circuit of the main MCU; The test backboard MCU module is used for receiving a test instruction from the main MCU; The system main MCU hardware composition module is used for testing the power supply of the backboard MCU and performing cascade communication test on the main MCU and the backboard MCU; the system main MCU hardware component module comprises a backboard voltage and current acquisition circuit unit, an RS485 cascade circuit unit, a load switching circuit unit and a power supply circuit unit; And the exploder backboard detection module is used for detecting and quality testing the production backboard.
2. The automated test system of claim 1 wherein the RTOS software image is comprised of two levels of firmware: (1) The bootstrap unit is powered on and runs to finish clock/peripheral minimum initialization, application program integrity verification and OTA upgrading, and after verification, the control right is handed over in a safe jump mode; (2) Application unit-integrate four co-task entities: a) The upper computer communication task is used for receiving and analyzing a self-defined instruction set, triggering a local IO (load, buzzer and indicator light) or sending an asynchronous request to other tasks according to an instruction code; b) The backboard communication task is fully duplex transmission with the backboard to be tested through a UART link, so that test instruction forwarding and response data stoping are realized; c) The cascade bus task supports a master/slave configurable mode through an RS-485 interface to complete multi-node cascade communication pressure test; d) The dynamic task scheduler dynamically starts and stops the tasks according to a test sequence issued by the upper computer based on a priority preemption and time slice rotation mixed algorithm, and uniformly manages shared resources through the mutex signal quantity and the message queue, thereby ensuring zero conflict and zero loss of test actions.
3. The automated testing system based on the upper computer backboard of claim 1, wherein the testing backboard MCU module realizes full-automatic adaptation and parallel scheduling by the following steps: S1, after test configuration, namely an upper computer is started, identifying and binding a target backboard type, and automatically loading a corresponding communication protocol stack; the user selects items according to the need in a graphical test unit library (at least integrating four atomic services of voltage and current collection, load switching, serial port transparent transmission and cascading test), and generates an extensible mark script by one key along with an execution sequence, a threshold window and hardware parameters; S2, issuing an instruction, namely compiling a script into an encrypted instruction frame by an upper computer, and sequentially delivering the encrypted instruction frame to a main MCU through a high-speed bus; S3, performing zero-blocking dynamic scheduling on the operation command sequence by a task scheduler of the dynamic scheduling-main control module based on a priority-time slice mixing algorithm, and ensuring that the multi-channel test actions are strictly executed in parallel according to time sequences.
4. The automated testing system based on the upper computer backboard of claim 3, wherein the main control module dynamically realizes sequential scheduling of task scheduler operation command sequences by: a. Calling a signal acquisition task to execute multichannel ADC sampling, and adopting algorithms such as mean value filtering and the like to process data; b. Invoking an IO control task, and driving a load circuit to switch to a specified mode; c. Transmitting a specific protocol frame to a tested backboard through a backboard communication task to perform functional test; d. carrying out cascade communication test with configurable master/slave mode with the tested backboard through cascade bus task; e. and in the result summarizing and feedback stage, each task returns an execution result (original data and a status code) to the main MCU, the main MCU reports the execution result to the upper computer, the upper computer analyzes the result according to the self-defined judgment logic, a structured test report (including each item of data, the self-defined error code and a final conclusion) is generated and displayed, the test result is sent to the main MCU, and the main MCU responds to the buzzer and prompts the indicator lamp.
5. The automated test system of back panel of host computer of claim 3, wherein said master control module performs zero-gap pipelined scheduling of the sequence of operation commands by means of a dynamic task scheduler, comprising the steps of: a) The signal acquisition-scheduler triggers the multi-channel ADC task and adopts algorithms such as mean value filtering and the like to process data; b) IO control, namely, immediately activating an IO task, switching a load circuit to an instruction specified working condition through a MOSFET array without disturbance, and driving the load circuit to be switched to a specified mode; c) Backboard communication-the dispatcher immediately issues a backboard communication task, and the communication task sends a specific protocol frame to the backboard to be tested to perform functional test; d) Cascade test-parallel or continuous starting cascade bus task, and finishing RS-485 link pressure and fault tolerance verification in a master/slave configurable role; e) The method comprises the steps of summarizing results, namely, returning original data and status codes at the atomic level of each task, packaging by a main MCU, reporting to an upper computer at a high speed, generating a structured test report by the upper computer according to user-defined judging logic, reversely issuing a conclusion frame, immediately driving a buzzer and an RGB indicator lamp after receiving by the main MCU, and completing one-time closed-loop feedback by sound-light combination.
6. The automatic testing system based on the upper computer backboard of claim 1, wherein the backboard voltage and current acquisition circuit unit is used for acquiring and testing the power supply, the bus communication voltage and the backboard power consumption of the backboard MCU; the RS485 cascade circuit unit is used for being responsible for cascade communication test of the main MCU and the backboard MCU; the load switching circuit unit is used for fixed resistance switching (255 omega, 1 Komega, 10 Komega), light-heavy load switching and bus short-circuit open-circuit switching of each gear; The power supply circuit unit is used for a main MCU power supply, a 2.5V reference power supply, an isolation power supply and a backboard MCU power supply.
7. The automatic testing system based on the upper computer backboard of claim 1, wherein the initiator backboard detection module comprises a semi-finished product detection unit and a finished product detection unit, the semi-finished product detection unit is used for detecting bare PCB of the backboard and mainly detecting backboard hardware performance such as power supply and bus communication voltage and current, and the finished product detection unit is used for detecting backboard after backboard assembly is completed and mainly detecting software functions such as serial port communication, cascade communication and analog load communication.
8. The automated testing system based on the upper computer backboard of claim 1, wherein the detecting backboard quality test comprises the following steps: Step 1, backboard type self-adaptive identification, namely automatically enumerating two topologies of a compatible backboard/group standard backboard after an upper computer is electrified, issuing a command to a main MCU according to the selected type, dynamically switching an internal DCDC by the main MCU, outputting a 5V or 8.5V accurate power supply, and realizing one-key compatibility of the same tool on a JQ and JWT electronic detonator backboard; Step 2, the workstation fingerprint configuration, namely inputting a workstation number, a factory code, a product identification number and a batch number in a window of an upper computer 'workstation configuration', splicing the fields into a unique equipment number SN according to a set protocol by the upper computer, writing the unique equipment number SN into a read-only memory area of a backboard MCU in a subsequent test flow, and completing product identity curing; step 3, flexibly checking test items, namely freely checking test sub-items in a semi-finished product station or a finished product station page by a user through a visual tree menu, and clicking 'save' to instantly generate an extensible test script; Step 4, setting index threshold value online, entering a test index configuration page, inputting upper and lower limits for each subitem, and simultaneously expanding derivative parameters such as delay, sampling points, fault tolerance times and the like to realize the multiplexing of multiple clients of the same script; Step 5, link self-detection, namely selecting a serial port of a tool main MCU, setting 115200bps baud rate, clicking 'checking', and ensuring zero packet loss of a communication link by two-way check of a handshake frame between an upper computer and the main MCU; Step 6, performing one-key start test and real-time diagnosis, namely clicking a start, sequentially issuing control instructions by an upper computer according to a script, sequentially executing atomic tests such as voltage sampling, load switching, bus cascading, detonator simulated ignition and the like by using a host MCU internal RTOS in a preemptive scheduling mode, and returning a result frame; Step 7, after batch-level statistics and acousto-optic prompt, namely all sub items are completed, the upper computer writes the PASS/FAIL result back to the main MCU, the main MCU drives the buzzer to visually distinguish qualification/failure by combining the number of 'drop-drop' times and RGB lamp colors, and meanwhile, the interface is rolled to refresh the accumulated test number, the qualification number and the qualification rate to complete batch-level quality portrait; And 8, reporting a block chain type certificate-HTML format test report, wherein the report includes a test time stamp, equipment SN, an index upper limit, an index lower limit, actual measurement data and a judgment conclusion, and synchronously archiving the test time stamp, the equipment SN, the index upper limit, the index lower limit, the actual measurement data and the judgment conclusion to a local database and a factory MES, so that the full life cycle traceability is realized.
9. The automated test system of claim 8, wherein step 4 further comprises the steps of: a. the backboard is electrified, and the upper computer waits for the communication time after the backboard is electrified; b. The back plate regulates the time required by the bus voltage, and the upper computer reads the bus voltage after waiting for the back plate regulating time; And c, APP jump time, wherein the back plate is provided with two application programs, namely JQ and JWT, when the back plate application programs are switched, the initialization time of each application program after the jump is inconsistent, and the upper computer needs to wait for the jump time and then start communication after switching the application programs.
10. The automated test system of claim 9, wherein step 4 further comprises the steps of: d. The short circuit voltage measurement time, the parameter is suitable for bus short circuit test, namely bus short circuit maintaining time, and the bus short circuit protection function of the backboard is mainly verified; e. Cascade test times, which are used for cascade communication test and can be configured according to the requirements; and f, EW software version, JQ software version and hardware version, wherein the parameter is the index of configuring the software and hardware version of the test backboard.

Description

Automatic testing system based on upper computer backboard Technical Field The invention belongs to the technical field of automatic testing of backboard, and particularly relates to an automatic testing system based on a backboard of an upper computer. Background In the production and quality inspection links of the back plate of the industrial electronic detonator initiator, the hardware performance (such as various paths of voltage, current, load driving capability and carrying capability) and software functions (such as serial port communication, cascade bus communication and memory read-write) of the back plate need to be comprehensively tested, most of the conventional test tools are special equipment for functional solidification, and the following obvious defects and limitations still exist: The flexibility is poor, the test flow and the project are fixed, and the quick change of the backboard of different models or the newly added test requirement can not be adapted; The degree of automation is limited, the switching among test items and the dynamic adjustment of test conditions (such as a load mode) depend on manual operation, so that the full-automatic test of complex sequences is difficult to realize, the efficiency is low and the error is easy to occur; The universality is not enough, one set of tooling is usually only aimed at a backboard with a specific model, so that the production line is required to be provided with various tooling, the management is complex, and the resource utilization rate is low. Therefore, the invention provides an automatic testing system based on the back plate of the upper computer. Disclosure of Invention In order to overcome the deficiencies of the prior art, at least one technical problem presented in the background art is solved. The technical scheme adopted by the invention for solving the technical problems is that the automatic testing system based on the back plate of the upper computer comprises the following components: The upper computer module is used for customizing test items, arranging test sequences, setting test parameters and judging rules, sequentially issuing configuration information to the main MCU, and providing a graphical test configuration interface; the main MCU module is used for testing and executing a core scheduler and running real-time operating system (RTOS) software; The test load module is used for connecting the two buses with the main MCU and the test backboard MCU, and is used for switching in various modes such as open circuit, short circuit, fixed resistance, simulated detonator load and the like according to the instruction of the upper computer through the load switching circuit of the main MCU; The test backboard MCU module is used for receiving a test instruction from the main MCU; The system main MCU hardware composition module is used for testing the power supply of the backboard MCU and performing cascade communication test on the main MCU and the backboard MCU; the system main MCU hardware component module comprises a backboard voltage and current acquisition circuit unit, an RS485 cascade circuit unit, a load switching circuit unit and a power supply circuit unit; And the exploder backboard detection module is used for detecting and quality testing the production backboard. Preferably, the RTOS software image is comprised of two levels of firmware: (1) The bootstrap unit is powered on and runs to finish clock/peripheral minimum initialization, application program integrity verification and OTA upgrading, and after verification, the control right is handed over in a safe jump mode; (2) Application unit-integrate four co-task entities: a) The upper computer communication task is used for receiving and analyzing a self-defined instruction set, triggering a local IO (load, buzzer and indicator light) or sending an asynchronous request to other tasks according to an instruction code; b) The backboard communication task is fully duplex transmission with the backboard to be tested through a UART link, so that test instruction forwarding and response data stoping are realized; c) The cascade bus task supports a master/slave configurable mode through an RS-485 interface to complete multi-node cascade communication pressure test; d) The dynamic task scheduler dynamically starts and stops the tasks according to a test sequence issued by the upper computer based on a priority preemption and time slice rotation mixed algorithm, and uniformly manages shared resources through the mutex signal quantity and the message queue, thereby ensuring zero conflict and zero loss of test actions. Preferably, the test backboard MCU module realizes full-automatic adaptation and parallel scheduling by the following steps: S1, after test configuration, namely an upper computer is started, identifying and binding a target backboard type, and automatically loading a corresponding communication protocol stack; the user selects items according to the