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CN-121978506-A - Small-step-distance wafer testing method and system

CN121978506ACN 121978506 ACN121978506 ACN 121978506ACN-121978506-A

Abstract

The application discloses a small-step-pitch wafer testing method and a small-step-pitch wafer testing system, and relates to the technical field of semiconductor testing. The method comprises the steps of obtaining an original step size of a wafer chip to be tested, dividing at least two adjacent chips into virtual test units according to the original step size and a minimum step threshold preset by test equipment, enabling the step size of the virtual test units to be not smaller than the minimum step threshold, controlling the test equipment to step according to the step size of the virtual test units, testing each chip in the virtual test units, encoding test results of each chip in the virtual test units into a combined identification value according to a preset encoding rule, recording the combined identification value to a wafer graph, and decoding the combined identification value according to a decoding rule to restore the test results of each chip. The application solves the problem that the test equipment is limited by mechanical stepping precision and cannot test the micro-size chip, reduces the equipment updating cost, and realizes the accurate test and data recording of the small-step product.

Inventors

  • WU JUN
  • PAN ZHIHUA
  • YUAN ZHIWEI

Assignees

  • 珠海市中芯集成电路有限公司

Dates

Publication Date
20260505
Application Date
20260212

Claims (10)

  1. 1. A small pitch wafer testing method, comprising: acquiring the original step size of chips on a wafer to be tested; Dividing at least two adjacent chips into virtual test units according to the original step size and a minimum step threshold preset by test equipment, wherein the step of each virtual test unit is not smaller than the minimum step threshold; The testing equipment is controlled to step according to the step distance of the virtual testing unit, and each chip in the virtual testing unit is tested to obtain the testing result of each chip; According to a preset coding rule, coding the test result of each chip in the virtual test unit into a combined identification value, and recording the combined identification value to a wafer map; And decoding the combined identification value in the wafer map according to a decoding rule corresponding to the encoding rule, and restoring the test result of each chip.
  2. 2. The method for testing a small pitch wafer according to claim 1, wherein the obtaining the original pitch size of the chips on the wafer to be tested comprises: acquiring a first original step distance of the chip in a first direction; Acquiring a second original step distance of the chip in a second direction; wherein the second direction is perpendicular to the first direction.
  3. 3. The method for testing a small pitch wafer according to claim 2, wherein dividing adjacent at least two chips into virtual test units according to the original pitch size and a minimum pitch threshold preset by a test device comprises: Determining a first combined number in the first direction when the first raw stride is less than the minimum stride threshold, such that a product of the first raw stride and the first combined number is not less than the minimum stride threshold; Determining a second combined number in the second direction when the second raw stride is less than the minimum stride threshold, such that a product of the second raw stride and the second combined number is not less than the minimum stride threshold; And dividing adjacent chips into the same virtual test unit according to the first combination quantity and the second combination quantity.
  4. 4. The small pitch wafer testing method according to claim 1, wherein the testing each of the chips in the virtual testing unit to obtain a test result of each of the chips comprises: simultaneously contacting all of the chips within the virtual test cell with a probe card, wherein the probe card comprises a probe set corresponding to all of the chips within the virtual test cell; And executing the test on all chips in the virtual test unit in parallel through a plurality of test channels of the tester, and obtaining the test result of each chip.
  5. 5. The method for testing a small pitch wafer according to claim 1, wherein the encoding the test result of each chip in the virtual test unit into a combined identification value according to a preset encoding rule includes: performing numerical conversion on the test results of each chip in the virtual test unit to obtain a state value corresponding to each chip; distributing corresponding coding parameters for each chip in the virtual test unit; and carrying out operation according to the state values of all the chips in the virtual test unit and the corresponding coding parameters to obtain the combined identification value.
  6. 6. The small pitch wafer test method as recited in claim 5, wherein the encoding parameter is a binary bit position; The operation is performed according to the state values of all the chips in the virtual test unit and the corresponding coding parameters to obtain the combined identification value, and the method comprises the following steps: Shifting the state value corresponding to each chip to the corresponding binary bit position; and carrying out summation operation on each shifted state value to obtain the combined identification value.
  7. 7. The method for testing a small pitch wafer according to claim 6, wherein performing numerical conversion on the test result of each chip in the virtual test unit to obtain a state value corresponding to each chip comprises: Subtracting a first preset value from the test result of each chip to obtain the state value corresponding to each chip; and performing summation operation on the shifted state values to obtain the combined identification value, and then further comprising: And adding a second preset value to the result of the summation operation to obtain a final combined identification value.
  8. 8. The method for testing a small-pitch wafer according to claim 7, wherein decoding the combined identification values in the wafer map according to a decoding rule corresponding to the encoding rule, and recovering the test result of each chip, comprises: Subtracting the second preset value from the combined identification value to obtain a decoding intermediate value; binary conversion is carried out on the decoding intermediate value to obtain a decoding binary value; Performing mask operation on the decoded binary values according to the coding parameters corresponding to the chips to obtain the state values of the chips; and adding the first preset value to the state value corresponding to each chip to obtain the test result corresponding to each chip.
  9. 9. The small-step wafer test method according to claim 1, wherein the encoding rule adopts a table look-up mapping mode; The step of encoding the test result of each chip in the virtual test unit into a combined identification value according to a preset encoding rule comprises the following steps: Establishing a mapping table between test result combinations and the combination identification values, wherein the mapping table records all possible combinations of the test results of all chips in the virtual test unit and the corresponding combination identification values; Obtaining the test results of the chips in the virtual test unit to form the test result combination; and searching the combination identification value corresponding to the test result combination in the mapping table.
  10. 10. A small pitch wafer testing system, comprising: the probe station is used for bearing a wafer to be tested and executing stepping movement; The probe card is arranged on the probe station and comprises a plurality of test positions, each test position corresponds to one virtual test unit, and each test position comprises a probe group corresponding to all chips in the virtual test unit; The testing machine is electrically connected with the probe card and is used for executing parallel test on the chips in the virtual testing unit through a plurality of testing channels; The computing module is used for acquiring the original step size of chips on a wafer to be tested, and dividing at least two adjacent chips into a virtual testing unit when the original step size is smaller than a minimum step threshold preset by testing equipment, so that the step size of the virtual testing unit is larger than or equal to the preset minimum step threshold; the test control module is used for controlling the probe station to move step by step according to the step size of the virtual test unit and controlling the test machine to perform parallel test on a plurality of chips contained in the same virtual test unit so as to obtain a test result of each chip; the data coding module is used for coding the test results of all chips in the same virtual test unit into a combined identification value by utilizing a preset coding rule, and recording the combined identification value to a wafer graph spectrum; and the data reduction module is used for decoding the combined identification value in the wafer map according to the decoding rule corresponding to the encoding rule, and reducing the test result of each chip.

Description

Small-step-distance wafer testing method and system Technical Field The application relates to the technical field of semiconductor testing, in particular to a small-step-distance wafer testing method and system. Background With the rapid development of semiconductor technology, the design size of integrated circuit chips has been increasingly miniaturized in order to reduce the manufacturing cost of individual chips and to improve the wafer utilization. In the subsequent semiconductor process, wafer testing is a critical ring, and the wafer is carried by the probe station to perform stepping movement, so that probes on the probe card are contacted with bonding pads of the chip, and the functional and electrical parameter testing is performed on the chip in cooperation with the tester. In conventional test flows, the step distance of the probe station is typically set to be consistent with the physical dimensions of the chip in order to traverse the chip one by one or in parallel. When the chip size on the wafer to be tested is smaller than the minimum step limit in the X direction or the Y direction, the probe station cannot set the effective step parameters, so that the equipment cannot perform normal step movement or cannot accurately align to the next chip to be tested. In response to this problem, the conventional solution in the industry is to eliminate old equipment and purchase a probe station with higher precision. The method has the advantages that equipment purchasing cost is high, the production cost of chips is obviously increased, and a large number of existing old-type probe stations in a factory are idle, so that great resource waste is caused. In addition, data logging challenges are faced when attempting to test in parallel across multiple small-sized chips by stepping at a time with existing devices. Standard wafer maps are typically based on a single coordinate system, i.e., one logical coordinate point can record only one test result. When a plurality of chiplets are combined into one test bit for testing, the existing test system cannot record and distinguish the independent test states of the plurality of chiplets on the same coordinate point at the same time, which can lead to confusion or loss of test data, so that the subsequent dicing and packaging process cannot accurately identify good products and defective products. Therefore, a technical scheme capable of realizing accurate test of small-size chips and accurately restoring test data of each chip on the premise of being compatible with the existing low-precision stepping probe station is needed. Disclosure of Invention The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a small-step-distance wafer testing method and a small-step-distance wafer testing system, which can break the hardware bottleneck that testing equipment cannot test a chip with a small size due to mechanical stepping precision limitation (such as minimum step distance limitation). In a first aspect, an embodiment of the present application provides a small pitch wafer testing method. The small-stride wafer testing method comprises the steps of obtaining an original stride size of chips on a wafer to be tested, dividing at least two adjacent chips into virtual testing units according to the original stride size and a minimum stride threshold preset by testing equipment, controlling the testing equipment to step according to the stride of the virtual testing units and test the chips in the virtual testing units to obtain testing results of the chips, encoding the testing results of the chips in the virtual testing units into combined identification values according to preset encoding rules, recording the combined identification values to a wafer map, decoding the combined identification values in the wafer according to decoding rules corresponding to the encoding rules, and restoring the testing results of the chips. The small-step-distance wafer testing method at least has the advantages that the small-step-distance wafer testing method is used for dividing at least two adjacent chips into virtual testing units according to the minimum step distance threshold preset by the testing equipment by acquiring the original step distance size of the chips on the wafer to be tested, so that the whole step distance of the virtual testing units is not smaller than the minimum step distance threshold of the equipment, and further the testing equipment is controlled to move step by taking the virtual testing units as units. The mechanism effectively breaks the hardware bottleneck that the existing test equipment such as the probe station cannot test the micro-size chip due to mechanical stepping precision limitation (such as minimum step distance limitation), so that the existing equipment can be used for testing small step distance products without purchasing high-precision new equipmen