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CN-121978509-A - Semiconductor material testing device and testing method

CN121978509ACN 121978509 ACN121978509 ACN 121978509ACN-121978509-A

Abstract

The invention relates to the technical field of semiconductors and discloses a semiconductor material testing device and a semiconductor material testing method. Handles at two ends of the integrated socket in the connecting assembly are pushed into the positioning groove, so that the integrated socket forms a stable locking state. The static characteristic de-embedding processing module establishes a static linear impedance mathematical model, extracts a static contact impedance constant and a static bias voltage, and the system performs de-embedding compensation calculation on the original response voltage by using the static contact impedance constant and the static bias voltage during formal test.

Inventors

  • LI FEILONG
  • BAO ZHIJIE

Assignees

  • 南京宏泰半导体科技股份有限公司

Dates

Publication Date
20260505
Application Date
20260330

Claims (10)

  1. 1. The semiconductor material testing device comprises a parameter analyzer (1), and is characterized in that a connecting component (2) is arranged at the lower part of the parameter analyzer (1), the right surface of the parameter analyzer (1) is electrically connected with a probe table (4) through a wire, and a protection containing component (3) is arranged at the right side of the parameter analyzer; The connecting assembly (2) comprises an integrated socket (201), a plurality of groups of integrated sockets (204) are formed in the front surface of the integrated socket (201), handles (202) are slidably connected to the left side and the right side of the front surface of the integrated socket (201), a dust-proof plate (203) is rotatably connected to the lower portion of the front surface of the parameter analyzer (1), and a positioning groove (205) is formed in the lower portion of the front surface of the parameter analyzer (1).
  2. 2. The semiconductor material testing device according to claim 1, wherein the protection storage component (3) comprises a separation plate (304), the outer surface of the separation plate (304) is fixedly connected with the parameter analyzer (1), a foam-rubber cushion (303) is fixedly connected to the inner side of the separation plate (304), a protection plate (301) is slidingly connected to the outer side of the separation plate (304), and a magnetic block (302) is fixedly connected to the upper end of the protection plate (301).
  3. 3. The semiconductor material testing device according to claim 1, wherein a rectangular chute is formed in the lower portion of the inner surface of the parameter analyzer (1), and a control panel is provided at the front surface of the parameter analyzer (1).
  4. 4. The semiconductor material testing device according to claim 1, wherein the left and right ends of the integrated socket (201) are slidably connected to the parameter analyzer (1), and the rear end of the integrated socket (201) is electrically connected to the parameter analyzer (1) through a wire.
  5. 5. The semiconductor material testing device according to claim 1, wherein the integrated socket (204) is configured as a butt joint, the handle (202) is integrally configured in a J shape, the positioning grooves (205) are provided with two groups, and the length and width dimensions of the cross sections of the two groups of positioning grooves (205) are the same as those of the handle (202).
  6. 6. The semiconductor material testing device according to claim 2, wherein a chute is formed on the right side of the partition plate (304), the outer surface of the foam-rubber cushion (303) is fixedly connected with the parameter analyzer (1), the outer surface of the protection plate (301) is slidably connected with the parameter analyzer (1), the front side and the rear side of the magnetic block (302) are slidably connected with the parameter analyzer (1), and a groove is formed on the right side of the parameter analyzer (1).
  7. 7. The semiconductor material testing device according to claim 2, wherein the sponge pad (303) is made of an antistatic polyurethane material with a conductive carbon film attached to the surface, the conductive carbon film at the bottom of the sponge pad (303) is connected with a grounding terminal of the parameter analyzer (1) through an internal metal wire, and a central control board, a high-frequency data acquisition module, a source measurement unit and a static feature de-embedding processing module for performing logic scheduling are integrated in the internal space of the parameter analyzer (1).
  8. 8. The semiconductor material testing device according to claim 7, wherein the source measuring unit employs a precision digital controlled constant current source and constant voltage source switching circuit with four-wire kelvin terminals electrically connected to the integrated socket (201) through internal shielded cables, and the static feature de-embedding processing module employs a field programmable gate array chip with a hardware multiplier-adder disposed therein.
  9. 9. A testing method of a semiconductor material testing apparatus, characterized in that the testing method is applied to the semiconductor material testing apparatus as claimed in any one of claims 1 to 8, the testing method comprising the steps of: S100, a mechanical boundary condition solidification and hardware conduction step, namely turning a dust-proof plate (203), pulling out an integrated socket (201), transversely pushing a handle (202) into a positioning groove (205), limiting and locking the integrated socket (201) to form a stable locking state, downwards sliding a protection plate (301), moving a probe table (4) out of a storage groove, adjusting the probe table (4) to enable the probe to be in contact with a semiconductor material, inserting a butt-plug connector at the rear end of the probe table (4) into an integrated socket (204) of the integrated socket (201), and completing physical communication of a test loop; S200, a static characteristic extraction step based on a least square method comprises the steps that a central control board sends an instruction to a source measurement unit, and the source measurement unit injects step-type calibration test current to a test loop; S300, a signal real-time de-embedding compensation and characteristic analysis step, wherein a source measurement unit applies formal test excitation current to a semiconductor material, and a high-frequency data acquisition module acquires original response voltage; S400, physical resetting and anti-collision sealing storage steps comprise the steps of pulling out the opposite plug type connector, pulling out the handle (202) from the positioning groove (205), pushing the integrated socket (201) back into the parameter analyzer (1) and closing the dust-proof plate (203), pushing the probe table (4) into the groove on the side surface of the parameter analyzer (1), enabling the top end of the probe table (4) to lean against the lower surface of the foam cushion (303), sliding the protection plate (301) downwards to a closed position, and keeping the protection plate (301) in a lower end closed state by means of self gravity.
  10. 10. The semiconductor material testing apparatus and the testing method according to claim 9, wherein in the step S200, the specific execution logic of the static feature extraction step is: The static characteristic de-embedding processing module establishes a static linear impedance mathematical model of the contact interface based on the static constant characteristics of the contact impedance; the static characteristic de-embedding processing module algebraic solves the static linear impedance mathematical model to calculate a static contact impedance constant and a static bias voltage; the central control board compares the absolute value of the static bias voltage with a preset safety threshold voltage, if the absolute value of the static bias voltage is larger than the safety threshold voltage, the central control board judges that a physical connection abnormal state exists and stops calibrating and testing control flow, and if the absolute value of the static bias voltage is smaller than or equal to the safety threshold voltage, the central control board judges that the mechanical locking state is safe and effective and solidifies static contact impedance constant and the static bias voltage.

Description

Semiconductor material testing device and testing method Technical Field The invention relates to the technical field of semiconductors, in particular to a semiconductor material testing device and a semiconductor material testing method. Background The semiconductor material testing device is basic detection equipment in the manufacturing and research links of semiconductor devices, and is mainly used for measuring and analyzing the electrical characteristics and physical parameters of semiconductor wafers, chips and novel film materials. The test system is generally composed of a parameter analyzer host computer which is responsible for outputting excitation signals and collecting response data, a probe station which is responsible for bearing samples to be tested and making probe contact, and a connecting interface and a cable assembly which are used for establishing a signal transmission path between the two. In the conventional testing process, a technician places a semiconductor material to be tested on an operating platform of a probe station and adjusts the micro-probe to make physical contact with a test electrode on the surface of the semiconductor material. And then, an operator acquires an external coaxial test cable, one end of the cable is connected to the signal leading-out end of the probe station, and the other end of the cable is directly inserted into the exposed test socket on the front panel of the parameter analyzer to establish a complete test path. After the hardware butt joint is finished, a technician sets a test threshold through a control panel of the parameter analyzer, starts the equipment to apply voltage or current excitation signals to the semiconductor material, synchronously records returned response electric signals, and finally performs basic mathematical conversion and chart output on the acquired data by means of a built-in general compensation model of the equipment. When the existing semiconductor material testing device is used for high-precision electrical measurement, the defects that the algorithm compensation is invalid and the measurement precision is limited due to dynamic fluctuation of interface contact impedance exist. The conventional plug-in butt joint structure is generally adopted by the conventional parameter analyzer interface, and the joint part lacks a stable mechanical limit design. In the whole test period, the external test cable is very easy to be influenced by environmental micro vibration or stress release of the cable, so that dynamic contact displacement occurs at a physical contact interface of the plug and the test socket. Such dynamic contact displacement causes the contact impedance at the interface to appear as an unpredictable random fluctuation variable. Due to the lack of absolute static physical boundary conditions, the existing test system cannot accurately establish a static feature model to extract a fixed contact impedance constant, so that the system cannot accurately execute de-embedding compensation calculation in a data processing stage to deduct impedance interference of external wiring. Dynamic errors which are difficult to eliminate are mixed in the electrical response data finally collected by the system, and the electrical response voltage of the semiconductor material cannot be truly restored. Disclosure of Invention In order to overcome the defects in the prior art, the invention provides a semiconductor material testing device and a testing method, which solve the problems mentioned in the background art. In order to achieve the above purpose, the invention is realized by the following technical scheme: The invention provides a semiconductor material testing device, which comprises a parameter analyzer, wherein a connecting component is arranged at the lower part of the parameter analyzer, a probe table is electrically connected to the right surface of the parameter analyzer through a wire, a protection storage component is arranged on the right side of the parameter analyzer, the connecting component comprises an integrated socket, a plurality of groups of integrated sockets are arranged on the front surface of the integrated socket, handles are slidingly connected to the left side and the right side of the front surface of the integrated socket, a dust-proof plate is rotatably connected to the lower part of the front surface of the parameter analyzer, a positioning groove is arranged on the lower part of the front surface of the parameter analyzer, the protection storage component comprises a separation plate, the outer surface of the separation plate is fixedly connected with the parameter analyzer, a sponge pad is fixedly connected to the inner side of the separation plate, a protection plate is slidingly connected to the outer side of the separation plate, and a magnetic block is fixedly connected to the upper end of the protection plate. A rectangular chute is arranged at the lower part of the inner surface of