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CN-121978512-A - Chip abnormal data stream detection early warning system and method based on integrated circuit

CN121978512ACN 121978512 ACN121978512 ACN 121978512ACN-121978512-A

Abstract

The invention discloses a chip abnormal data stream detection early warning system and method based on an integrated circuit, and relates to the technical field of chip detection; the method comprises the steps of extracting chip detection flow and detection link data for detecting abnormal events, analyzing key detection links influencing detection of the abnormal events based on the detection link data, judging the association relation between functional detection data and application performance detection data after first application in the detection abnormal events of similar chips, adjusting sampling frequency of various chips based on the association relation, acquiring normal detection events, verifying abnormal detection stability of the chip detection events after adjustment corresponding to the chip types, adjusting sampling data of the normal detection events, and feeding back to a detection flow management system. The whole analysis efficiency is improved, and the detection cost is optimized.

Inventors

  • YUAN YONGBIN

Assignees

  • 知码芯(杭州)电子科技有限公司

Dates

Publication Date
20260505
Application Date
20251201

Claims (10)

  1. 1. The chip abnormal data stream detection and early warning method based on the integrated circuit is characterized by comprising the following steps of: s1, acquiring chip detection events of an integrated circuit, extracting sampling data of functional detection data after the production of the integrated circuit is completed and corresponding application performance detection data after the first application; S2, extracting a chip detection flow for detecting abnormal events and detection link data, analyzing key detection links influencing detection of the abnormal events based on the detection link data; S3, judging the association relation between the function detection data and the application performance detection data after the first application in the detection abnormal event of the similar chips, and adjusting the sampling frequency of the test of the various chips based on the association relation; s4, acquiring a normal state detection event, verifying the abnormal detection stability of the chip detection event after adjustment corresponding to the chip type, adjusting sampling data of the normal state detection event, and feeding back to a detection flow management system.
  2. 2. The method for detecting and early warning abnormal data flow of chip based on integrated circuit according to claim 1, wherein in S1, the method comprises the following steps: S101, extracting chip detection events from a chip detection event database of an integrated circuit, wherein each chip detection event comprises sampling data of functional detection data after production is completed and corresponding application performance detection data after first application, the functional detection data comprises electrical parameters and functional test results, the electrical parameters comprise voltage, current and frequency, the functional test results comprise passing or failure indexes, the application performance detection data comprises field application performance and reliability indexes, the field application performance comprises power consumption, temperature and response time, the reliability indexes comprise service lives, and the functional detection data and the application performance detection data are subjected to data cleaning and normalization processing respectively; The method comprises the steps of S102, training a multiple linear regression model based on data of historical chip detection events, wherein DF k =W×DS k +b is used for detecting, DF k is used for representing a data vector formed by functional detection data of the kth chip detection event, DS k is used for representing a data vector formed by application performance detection data of the kth chip detection event, W is used for representing a weight matrix, b is used for representing a bias vector, the weight matrix and the bias vector are solved through a least square method, euclidean distance analysis is used for each chip detection event for analyzing errors between a multiple linear regression model predicted value and a data vector formed by actually measured application performance detection data, and if the errors are larger than an error threshold, the corresponding chip detection event is marked as detection abnormality, and a detection abnormal event list is generated.
  3. 3. The method for detecting and early warning abnormal data flow of chip based on integrated circuit according to claim 2, wherein in S2, the method comprises the following steps: S201, extracting a chip detection flow and detection link data of each detection abnormal event from a detection abnormal event list, and constructing a detection link data matrix; the chip detection flow comprises, but is not limited to, testing, calibrating and verifying links, wherein each link relates to a plurality of detection parameters including voltage, current or delay time, performing principal component analysis on a detection link data matrix, calculating a covariance matrix of the detection link data matrix, performing feature decomposition on the covariance matrix to obtain a feature value set and a corresponding feature vector set, wherein feature values are arranged in descending order, the feature vectors represent the direction of the principal component, summing the first r feature values in the feature value set and dividing the sum of the feature values by the total feature value to be marked as an accumulated contribution rate, selecting the smallest r to enable the accumulated contribution rate to exceed a preset threshold, and reserving the first r feature values and the corresponding feature vectors to generate a preferred feature value set and a corresponding preferred feature vector set; S202, analyzing the contribution degree of each detection link based on the preferred feature value set and the corresponding preferred feature vector set, wherein the contribution degree of the detection links is equal to the sum of products of absolute values of components of the preferred feature vectors in the corresponding detection links and the corresponding feature values, taking the median of all the contribution degrees as a contribution degree threshold value, marking the detection links with the contribution degrees larger than the contribution degree threshold value as key detection links, and generating a key detection link list.
  4. 4. The method for detecting and early warning abnormal data flow of chip based on integrated circuit according to claim 3, wherein in S3, the method comprises the following steps: S301, classifying chips according to a chip detection flow, wherein the chips in the same detection flow belong to the same class, extracting functional detection data of the chips adopting the detection flow and application performance detection data after first application from a detection abnormal event list for each class of chips, constructing a functional detection data matrix and an application performance detection data matrix, wherein rows in the functional detection data matrix represent detection abnormal events, and represent corresponding electrical parameters and functional test results; S302, constructing a process multiple linear regression model based on a function detection data matrix and an application performance detection data matrix of each type of chip, wherein the training mode of the process multiple linear regression model is the same as that of the detection multiple linear regression model; If the association degree is larger than the association degree threshold value, judging that the association degree is strong, reducing the sampling frequency of the test after the first application for the chip class with the strong association relation, and improving the sampling frequency of the test after the first application for the chip class without the strong association relation.
  5. 5. The method for detecting and early warning abnormal data flow based on integrated circuit according to claim 4, wherein in S4, the method comprises the following steps: S401, removing the events in the abnormal event detection list from the historical chip detection events, marking the rest events as normal detection events to form a normal detection event set, and analyzing a data adjustment factor based on the statistical characteristics of the abnormal event detection list and the normal detection event set, wherein the data adjustment factor is equal to the sum of the normal detection events divided by the normal detection events; S402, scaling continuous data points in a normal detection event set according to a data adjustment factor, adopting boundary truncation when the adjusted numerical value exceeds a preset data maximum operation range, taking the data adjustment factor as a discrete data point retention probability for discrete detection data, carrying out Bernoulli test on each discrete data point, retaining the discrete data points when a value generated by a random number generator is smaller than the data adjustment factor, otherwise removing the discrete data points, filling the removed discrete data points by adopting weighted summation of similar original data points, and generating an adjusted sampling data set; the discrete detection data comprises, but is not limited to, a pass or fail indicator; S403, setting a normal operation range for each detection parameter based on historical normal detection data, wherein the normal operation range is a mean value of parameter historical data plus or minus a plurality of standard deviations for continuous data, the normal operation range is a passing state for discrete detection data, and an abnormal detection stability index is calculated for each chip type, wherein the abnormal detection stability index is equal to the ratio of the number of data points of the chip type in the normal operation range in a sampling data set to the number of samples of the chip type in the sampling data set; Based on the abnormal detection stability index, the chip types in the normal detection event set are divided into different stability grades, and the sampling frequency is adjusted according to the stability grades.
  6. 6. The chip abnormal data flow detection and early warning system based on the integrated circuit is applied to the chip abnormal data flow detection and early warning method based on the integrated circuit, which is realized by any one of claims 1-5, and is characterized by comprising a detection abnormal analysis module, a key detection analysis module, a correlation analysis module and a normal state adjustment module; The detection abnormality analysis module is used for acquiring chip detection events of the integrated circuit, extracting sampling data of functional detection data after the production of the integrated circuit is completed and corresponding application performance detection data after the first application; the key detection analysis module is used for extracting a chip detection flow for detecting abnormal events and detection link data, analyzing key detection links influencing abnormal detection based on the detection link data, and analyzing the key detection links; The association analysis module is used for judging the association relation between the functional detection data and the application performance detection data after the first application in the detection abnormal event of the similar chips, and adjusting the sampling frequency of the test of various chips based on the association relation; the normal state adjusting module is used for acquiring normal state detection events, verifying abnormal detection stability of the adjusted chip detection events corresponding to the chip types, adjusting sampling data of the normal state detection events, and feeding back the sampling data to the detection flow management system.
  7. 7. The chip abnormal data stream detection and early warning system based on the integrated circuit of claim 6, wherein the detection and abnormal analysis module comprises a detection data acquisition unit and a difference analysis unit; The detection data acquisition unit is used for extracting chip detection events from a chip detection event database of the integrated circuit, and respectively carrying out data cleaning and normalization processing on the functional detection data and the application performance detection data; The difference analysis unit is used for training and detecting a multiple linear regression model based on data of historical chip detection events, analyzing errors between a predicted value of the multiple linear regression model and a data vector formed by actually measured application performance detection data by using Euclidean distance for each chip detection event, and marking the corresponding chip detection event as detection abnormality and generating a detection abnormality event list if the errors are larger than an error threshold.
  8. 8. The chip abnormal data stream detection and early warning system based on the integrated circuit of claim 6, wherein the key detection and analysis module comprises a feature screening unit and a contribution analysis unit; The feature screening unit is used for extracting chip detection flow and detection link data of each detection abnormal event from the detection abnormal event list to construct a detection link data matrix, carrying out principal component analysis on the detection link data matrix, calculating a covariance matrix of the detection link data matrix, carrying out feature decomposition on the covariance matrix to obtain a feature value set and a corresponding feature vector set, wherein the feature values are arranged in descending order, the feature vectors represent the direction of the principal component, summing the first r feature values in the feature value set and dividing the sum of the feature values by the total feature value to be marked as an accumulated contribution rate, selecting the smallest r to enable the accumulated contribution rate to exceed a preset threshold, and reserving the first r feature values and the corresponding feature vectors to generate a preferred feature value set and a corresponding preferred feature vector set; The contribution analysis unit is used for analyzing the contribution degree of each detection link based on the preferred feature value set and the corresponding preferred feature vector set, taking the median of all the contribution degrees as a contribution degree threshold value, marking the detection links with the contribution degree larger than the contribution degree threshold value as key detection links, and generating a key detection link list.
  9. 9. The integrated circuit based chip abnormal data stream detection and early warning system according to claim 6, characterized in that the association analysis module comprises a data matrix construction unit and an association judgment unit; The data matrix construction unit is used for classifying the chips according to the chip detection flow, and the chips in the same detection flow belong to the same class; for each type of chip, extracting the function detection data and the application performance detection data after the first application of the chip adopting the detection flow from a detection abnormal event list; The association judging unit is used for constructing a process multiple linear regression model based on the function detection data matrix and the application performance detection data matrix of each type of chip, analyzing the association degree based on the process multiple linear regression model, judging that the association degree is strong association if the association degree is larger than an association degree threshold value, reducing the sampling frequency of the test after the first application for the chip class with the strong association relation, and improving the sampling frequency of the test after the first application for the chip class without the strong association relation.
  10. 10. The chip abnormal data stream detection and early warning system based on the integrated circuit of claim 6, wherein the normal state adjustment module comprises a data adjustment factor analysis unit, a data adjustment unit and a detection adjustment unit; the data adjustment factor analysis unit is used for removing the events in the abnormal event list from the historical chip detection events, marking the rest events as normal detection events and forming a normal detection event set; The data adjustment unit is used for scaling continuous data points in the normal detection event set according to a data adjustment factor, adopting boundary truncation when the adjusted numerical value exceeds a preset data maximum operation range, taking the data adjustment factor as a discrete data point retention probability for discrete detection data, carrying out Bernoulli test on each discrete data point, retaining the discrete data point when the value generated by the random number generator is smaller than the data adjustment factor, otherwise removing the discrete data point, filling the removed discrete data point by adopting the weighted summation of similar original data points, and generating an adjusted sampling data set; The detection adjustment unit is used for setting a normal operation range for each detection parameter based on historical normal detection data, calculating an abnormal detection stability index for each chip type, dividing the chip types in the normal detection event set into different stability grades based on the abnormal detection stability index, and adjusting the sampling frequency according to the stability grades.

Description

Chip abnormal data stream detection early warning system and method based on integrated circuit Technical Field The invention relates to the technical field of chip detection, in particular to a chip abnormal data stream detection early warning system and method based on an integrated circuit. Background In the field of integrated circuit fabrication, after the chip is packaged, it must undergo strict production tests and performance verification to ensure that its function and reliability meet design criteria. However, with the increase of the complexity of the chip and the diversification of the application scenario, the conventional method gradually exposes the inherent limitations thereof. The existing detection strategy lacks intelligent resource allocation capability, so that the efficiency is low. Traditional sampling schemes and detection flow parameters are often statically set based on historical experience, and cannot be dynamically adjusted according to real-time data flows and actual risks of different product lines. This results in the inability to accurately target the weakest link and the highest risk product type, resulting in resource mismatch. On the one hand, the chip with stable performance and strong predictability can be subjected to excessive test, thereby increasing unnecessary cost, and on the other hand, the chip with high risk which really needs to be concerned can have detection blind areas. Therefore, the invention discloses a chip abnormal data stream detection and early warning system and method based on an integrated circuit to solve the problems. Disclosure of Invention The invention aims to provide a chip abnormal data stream detection early warning system and method based on an integrated circuit, so as to solve the problems in the prior art. In order to achieve the purpose, the invention provides the following technical scheme that the chip abnormal data stream detection and early warning method based on the integrated circuit comprises the following steps: s1, acquiring chip detection events of an integrated circuit, extracting sampling data of functional detection data after the production of the integrated circuit is completed and corresponding application performance detection data after the first application; S2, extracting a chip detection flow for detecting abnormal events and detection link data, analyzing key detection links influencing detection of the abnormal events based on the detection link data; S3, judging the association relation between the function detection data and the application performance detection data after the first application in the detection abnormal event of the similar chips, and adjusting the sampling frequency of the test of the various chips based on the association relation; s4, acquiring a normal state detection event, verifying the abnormal detection stability of the chip detection event after adjustment corresponding to the chip type, adjusting sampling data of the normal state detection event, and feeding back to a detection flow management system. According to the above, in S1, the following are included: S101, extracting chip detection events from a chip detection event database of an integrated circuit, wherein each chip detection event comprises sampling data of functional detection data after production is completed and corresponding application performance detection data after first application, the functional detection data comprises electrical parameters and functional test results, the electrical parameters comprise voltage, current and frequency, the functional test results comprise passing or failure indexes, the application performance detection data comprises field application performance and reliability indexes, the field application performance comprises power consumption, temperature and response time, the reliability indexes comprise service lives, and the functional detection data and the application performance detection data are subjected to data cleaning and normalization processing respectively; The method comprises the steps of S102, training a multiple linear regression model based on data of historical chip detection events, wherein DF k=W×DSk +b is used for detecting, DF k is used for representing a data vector formed by functional detection data of the kth chip detection event, DS k is used for representing a data vector formed by application performance detection data of the kth chip detection event, W is used for representing a weight matrix, b is used for representing a bias vector, the weight matrix and the bias vector are solved through a least square method, euclidean distance analysis is used for each chip detection event for analyzing errors between a multiple linear regression model predicted value and a data vector formed by actually measured application performance detection data, and if the errors are larger than an error threshold, the corresponding chip detection event is marked as detecti