CN-121978671-A - DSP engineering design system for space-borne radar temporary space target detection processing algorithm

CN121978671ACN 121978671 ACN121978671 ACN 121978671ACN-121978671-A

Abstract

The invention discloses a DSP engineering design system of a satellite-borne radar temporary target detection processing algorithm, which is realized by adopting a TI C66x series multi-core DSP, wherein the system is used for receiving input radar system parameters, receiving input processing mode configuration instructions, entering a designated processing mode according to the processing mode configuration instructions, acquiring original echo data of a stored target after entering the designated processing mode, and carrying out cooperative parallel processing of the original echo data by utilizing a plurality of cores in the multi-core DSP according to algorithm codes corresponding to the designated processing mode to obtain a target detection result. The invention realizes the multi-algorithm engineering realization scheme for detecting the temporary space target by the spaceborne radar through the multi-core DSP single board, can overcome the limitations of insufficient motion compensation precision and incomplete processing flow in the prior art, and can reduce the resource consumption and the operation time.

Inventors

YANG ZHIWEI
Song Jinheng
XU XINGYUAN
LI XIANGHAI
LV PENG

Assignees

西安电子科技大学

Dates

Publication Date: 20260505
Application Date: 20260108

Claims (10)

1. A DSP engineering design system for a satellite-borne radar temporary space target detection processing algorithm is characterized by being realized by adopting a TI C66x series multi-core DSP, and the system is used for: receiving input radar system parameters; Receiving an input processing mode configuration instruction, and entering a designated processing mode according to the processing mode configuration instruction; After entering the appointed processing mode, acquiring original echo data of a stored target, and carrying out cooperative parallel processing on the original echo data by utilizing a plurality of cores in the multi-core DSP according to an algorithm code corresponding to the appointed processing mode to obtain a target detection result; The system comprises six processing modes, wherein the first processing mode is used for determining a target detection result based on an MTD method and original echo data of the target in the case that the target does not generate distance walk, the second processing mode is used for determining the target detection result based on a one-dimensional filter bank and the original echo data of the target in the case that the target generates linear distance walk, the third processing mode is used for determining the target detection result based on a first-order KT transformation and the original echo data of the target in the case that the target generates linear distance walk, distance bending and Doppler frequency diffusion, the fourth processing mode is used for determining the target detection result based on a two-dimensional filter bank and the original echo data of the target in the case that the target generates linear distance walk, distance bending and Doppler frequency diffusion, the fifth processing mode is used for determining the target detection result based on a first-order KT transformation, a method matched quadratic term and the original echo data of the target in the case that the target generates linear distance walk, distance bending and three-order Doppler frequency diffusion, and the fifth processing mode is used for determining the target detection result based on a frequency domain GRFT method, the MTD method and the original echo data of the target in the case that the target generates linear distance walk, distance bending and Doppler frequency diffusion.
2. The DSP engineering design system for the space-borne radar temporary target detection processing algorithm according to claim 1, wherein the multi-Core DSP comprises eight cores from Core0 to Core7, each Core acquires a part of original echo data after entering the specified processing mode, processes the part of original echo data according to the algorithm corresponding to the specified processing mode to obtain a CFAR detection result, and any one of the eight cores performs calculation of target parameters according to the algorithm corresponding to the specified processing mode to obtain a target detection result, wherein the part of original echo data acquired by each Core is one eighth of the original echo data of the target.
3. The DSP engineering design system for a satellite borne radar null target detection algorithm according to claim 1, wherein the process of determining the target detection result based on the one-dimensional filter bank and the original echo data of the target in the case that the target generates linear distance walk includes: Acquiring original echo data and generating a conjugate reference signal, wherein the original echo data is echo data under the condition that a target generates linear distance walk; performing FFT (fast Fourier transform) on each pulse of the acquired original echo data to obtain pulse compressed data, and multiplying the pulse compressed data point by the conjugated reference signal to realize matched filtering to obtain matched filtered data; Performing fuzzy number compensation on the data after matching and filtering, and performing first-order linear distance walk correction on the data after fuzzy number compensation by a distance gate to obtain distance frequency domain-azimuth domain data; Performing IFFT (inverse fast Fourier transform) on the distance frequency domain-azimuth domain data pulse by pulse to obtain distance-azimuth time domain data; performing FFT (fast Fourier transform) on the distance-azimuth time domain data by distance gate to obtain distance-Doppler domain data; performing CFAR detection on the distance-Doppler domain data by distance gate to obtain a CFAR detection result; And carrying out target parameter calculation on the CFAR detection result to obtain a target detection result.
4. The DSP engineering design system of the space-borne radar null-target detection processing algorithm according to claim 1, wherein the determining the target detection result based on the first-order KT algorithm and the original echo data of the target in the case that the target generates linear distance walk comprises: Acquiring original echo data and generating a conjugate reference signal, wherein the original echo data is echo data under the condition that a target generates linear distance walk; performing FFT (fast Fourier transform) on each pulse of the acquired original echo data to obtain pulse compressed data, and multiplying the pulse compressed data point by the conjugated reference signal to realize matched filtering to obtain matched filtered data; Performing fuzzy number compensation on the data after the matching filtering, and performing Keystone transformation based on CZT on the data after the fuzzy number compensation by a distance gate to obtain distance frequency domain-azimuth domain data; Performing IFFT (inverse fast Fourier transform) on the distance frequency domain-azimuth domain data pulse by pulse to obtain distance-azimuth time domain data; performing FFT (fast Fourier transform) on the distance-azimuth time domain data by distance gate to obtain distance-Doppler domain data; performing CFAR detection on the distance-Doppler domain data by distance gate to obtain a CFAR detection result; And carrying out target parameter calculation on the CFAR detection result to obtain a target detection result.
5. The DSP engineering design system of the satellite borne radar null target detection processing algorithm according to claim 1, wherein the determining the target detection result based on the two-dimensional filter bank and the original echo data of the target in the case that the target generates linear distance walk, distance bend, and doppler frequency spread comprises: acquiring original echo data and generating a conjugate reference signal, wherein the original echo data is echo data under the conditions that a target generates linear distance walking, distance bending and Doppler frequency diffusion; performing FFT (fast Fourier transform) on each pulse of the acquired original echo data to obtain pulse compressed data, and multiplying the pulse compressed data point by the conjugated reference signal to realize matched filtering to obtain matched filtered data; Performing fuzzy number compensation on the data after matching and filtering, and performing first-order linear distance walk correction on the data after fuzzy number compensation by a distance gate to obtain distance frequency domain-azimuth domain data; Performing IFFT (inverse fast Fourier transform) on the distance frequency domain-azimuth domain data pulse by pulse to obtain distance-azimuth time domain data; compensating the quadratic term coefficient of the distance-azimuth time domain data by a distance gate to obtain echo data after secondary phase matching; performing FFT conversion on the echo data subjected to the secondary phase matching by a distance gate to obtain echo data subjected to azimuth FFT; Performing CFAR detection on the echo data subjected to azimuth FFT by distance gate to obtain a CFAR detection result; And carrying out target parameter calculation on the CFAR detection result to obtain a target detection result.
6. The DSP engineering design system of the space-borne radar space-facing target detection processing algorithm according to claim 1, wherein the determining the target detection result based on the first order KT transform, the method of matching the quadratic term, and the original echo data of the target in the case that the target generates linear distance walk, distance bend, and doppler frequency spread includes: acquiring original echo data and generating a conjugate reference signal, wherein the original echo data is echo data under the conditions that a target generates linear distance walking, distance bending and Doppler frequency diffusion; performing FFT (fast Fourier transform) on each pulse of the acquired original echo data to obtain pulse compressed data, and multiplying the pulse compressed data point by the conjugated reference signal to realize matched filtering to obtain matched filtered data; Performing fuzzy number compensation on the data after the matching filtering, and performing Keystone transformation based on CZT on the data after the fuzzy number compensation by a distance gate to obtain distance frequency domain-azimuth domain data; Performing IFFT (inverse fast Fourier transform) on the distance frequency domain-azimuth domain data pulse by pulse to obtain distance-azimuth time domain data; compensating the quadratic term coefficient of the distance-azimuth time domain data by a distance gate to obtain echo data after secondary phase matching; performing FFT conversion on the echo data subjected to the secondary phase matching by a distance gate to obtain echo data subjected to azimuth FFT; Performing CFAR detection on the echo data subjected to azimuth FFT by distance gate to obtain a CFAR detection result; And carrying out target parameter calculation on the CFAR detection result to obtain a target detection result.
7. The DSP engineering design system of the space-borne radar null target detection processing algorithm according to claim 1, wherein the determining the target detection result based on the frequency domain GRFT method, the MTD method, and the original echo data of the target in the case that the target generates distance walk and doppler frequency spread including the secondary phase and the tertiary phase includes: Acquiring original echo data and generating a conjugate reference signal, wherein the original echo data is echo data under the conditions that a target generates linear distance walking, distance bending and third-order Doppler frequency diffusion; performing FFT (fast Fourier transform) on each pulse of the acquired original echo data to obtain pulse compressed data, and multiplying the pulse compressed data point by the conjugated reference signal to realize matched filtering to obtain matched filtered data; Performing distance bending correction on the data after the matching filtering by distance gate to obtain data after the distance bending correction; performing IFFT (inverse fast Fourier transform) on the data subjected to the distance bending correction pulse by pulse to obtain distance-azimuth time domain data, wherein the distance-azimuth time domain data is in a complex form; Calculating the amplitude phase of the complex number, performing 2 pi remainder on the calculated phase to obtain a new phase, multiplying the new phase with the amplitude of the complex number, and then converting the multiplication result into float data to obtain initially optimized distance-azimuth time domain data; The phase of the initially optimized distance-azimuth time domain data is defined by a double type, then 2 pi is subjected to remainder of the phase defined by the double type so that the range of the phase is between [ -pi, pi ], and the remainder of the phase is converted into float data to obtain the distance-azimuth time domain data with optimized word length; compensating the quadratic term coefficient of the distance-azimuth time domain data subjected to word length optimization by using a compensation function of the determined float type, and obtaining echo data subjected to secondary phase matching; Compensating the third term coefficient for the echo data subjected to the second phase matching by a distance gate to obtain echo data subjected to the third phase matching; Performing FFT (fast Fourier transform) on the echo data subjected to the three phase matching by distance gate to obtain distance-Doppler domain data; performing CFAR detection on the distance-Doppler domain data by distance gate to obtain a CFAR detection result; And carrying out target parameter calculation on the CFAR detection result to obtain a target detection result.
8. The DSP engineering design system of claim 1, wherein each core sets a source address step size to be the size of each element in each row of a matrix to be transposed, sets a destination address step size to be the product of the length of the row and the size of the element, and completes the transposed operation of an entire row of elements by a single DMA operation, sets a source address step size to be the product of the length of the column and the size of the element for each element in each column of the matrix to be transposed, sets a destination address step size to be the size of the element, and completes the transposed operation of an entire column of elements by a single DMA operation when each core performs the matrix transposed operation.
9. The DSP engineering design system of the space-borne radar temporary space target detection processing algorithm according to claim 2 is characterized in that each core corresponds to one semaphore, the eight cores are different in one-to-one correspondence and independent of each other, the eight cores perform multi-core synchronization through the eight semaphores, the eight semaphores are 8 hardware semaphores arbitrarily selected from 64 independent hardware semaphores of the multi-core DSP, when the eight cores perform each multi-core operation task in each processing mode, each core applies for the corresponding semaphore through a semaphore application function, when the corresponding semaphore is in an idle state, the corresponding semaphore is marked as an occupied state, whether the corresponding semaphore of the remaining cores is marked as the occupied state or not is continuously detected, after the eight cores jointly detect that the eight semaphores are marked as the occupied state, the eight cores complete the current multi-core operation task, after that, each core releases the corresponding semaphore through a semaphore release function, so that the corresponding cores reset from the corresponding cores to the eight cores to the idle state, and continuously detect whether the corresponding semaphore is in the idle state, and reset to the idle state when the corresponding cores are reset to the eight cores, the corresponding to the idle state.
10. The engineering design system of the satellite-borne radar temporary space target detection processing algorithm DSP according to claim 2 is characterized in that on-chip memories L1D and L1P of the multi-core DSP are 32K caches, codes corresponding to the six processing modes are stored in an on-chip memory L2, L2 is set to be SRAM, and the original echo data are stored in an off-chip memory DDR 3.

Description

DSP engineering design system for space-borne radar temporary space target detection processing algorithm Technical Field The invention belongs to the technical field of radars, and particularly relates to a DSP engineering design system for a satellite-borne radar temporary space target detection processing algorithm. Background As a key component of space situation awareness and national security defense system, the spaceborne radar carries important tasks for effectively finding, tracking and identifying the airborne high-speed target. However, extremely high relative motion exists between the radar platform and the detected target, so that a phenomenon that a target echo signal received by the radar moves away from a unit obviously in a distance dimension occurs, doppler frequency shift is generated, the relativity between radar pulses is seriously destroyed, the echo energy of the target cannot be effectively focused on a distance-Doppler two-dimensional plane, the loss of signal to noise ratio is large, the detection probability of the target by the radar is rapidly reduced, and even the detection cannot be performed at all. Therefore, the echo signal is subjected to motion compensation through an improved coherent accumulation algorithm, and the method is a key step for realizing effective accumulation detection of the temporary empty target. While the conventional typical algorithms are theoretically complete and proved to be effective in academic research to solve the problem of detecting a high maneuvering target, the problem of computational efficiency is generally existed in practical engineering application, for example, the Keystone transformation needs to perform intensive interpolation operation in a high-dimensional space, and the operational complexity of GRFT increases exponentially with the parameter searching dimension and searching range. Especially matrix operations and data buffering under a large amount of observation data, the real-time requirement of signal processing is more challenging. On one hand, researchers reduce the computational complexity by improving the algorithm performance, on the other hand, the prior art improves the high-speed hardware platform to improve the computational efficiency, wherein the DSP performs the optimization design on the signal processing operation, has the characteristics of high efficiency, low power consumption and radiation resistance, and has the advantages in the aspects of complex, flexible and high-precision algorithm realization, but under the condition that the space-borne radar platform resources are severely limited (including computational resources, memory bandwidth and the like) and have strict requirements on the real-time performance of target detection, how to reasonably transplant the coherent accumulation algorithm and deeply optimize the hardware platform resources, so that the algorithm can efficiently and stably run on the space-borne DSP platform, and is still a key factor for limiting the space-borne radar to realize breakthrough of the temporary target detection capability. When an empty target (such as a hypersonic aircraft, a cruise missile and the like) is detected by the space-based early warning radar, due to extremely high relative speed, high-order motion and the like between the target and a radar platform, serious distance walking and Doppler frequency diffusion phenomena can be generated under the condition that the radar is accumulated in a coherent manner for a long time, and the accumulated target energy is diffused along the distance dimension and the Doppler dimension respectively, so that the output signal-to-noise ratio is reduced, and the Moving Target Detection (MTD) performance of the space-based radar is reduced. In order to solve the problems, complex coherent accumulation algorithms are generally adopted in the current field to perform motion compensation and energy accumulation on a target, and typical algorithms include Keystone Transformation (KT) based on linear scale expansion transformation, generalized Radon Fourier Transformation (GRFT) based on three-dimensional parameter joint search and the like. However, although these methods have a complete effect in theory, they generally require frequent large-scale matrix operations and data exchanges in engineering practice, and have a problem of high operation complexity. Currently, a high-performance multi-core Digital Signal Processor (DSP) is generally adopted as a core operation unit for the severe requirements of a space-based radar signal processing hardware platform in the aspects of reliability, power consumption, irradiation resistance, complex multi-algorithm tasks and the like. DSP has powerful signal processing capabilities, but its computing resources, memory bandwidth, and storage capacity remain severely limited. If the algorithm is directly implemented on the on-board DSP, the method faces serious engineering challenges such as i