CN-121978872-A - Overlay accuracy monitoring structure, monitoring method, semiconductor structure and manufacturing method thereof

CN121978872ACN 121978872 ACN121978872 ACN 121978872ACN-121978872-A

Abstract

The invention provides an overlay accuracy monitoring structure, a monitoring method, a semiconductor structure and a manufacturing method thereof, wherein an overlay accuracy monitoring structure is constructed, and the overlay accuracy can be monitored through the overlay accuracy monitoring structure, so that the overlay accuracy of a photoetching process in an ion implantation process can be conveniently and reliably obtained. In the formation process of the body region of the LDMOS device, although only a part of a required structure is formed through the body region photomask, the overlay accuracy of the photoetching process can be monitored through the overlay accuracy monitoring structure, so that the performance and the reliability of the formed LDMOS device can be improved.

Inventors

LI ZHONGREN
ZHAO XIAOYAN
He Fuxiu

Assignees

芯联集成电路制造股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260317

Claims (11)

1. The utility model provides an overlay accuracy control structure which characterized in that, overlay accuracy control structure includes: The first ion implantation structure is of a first conductivity type, and is provided with a strip-shaped implantation target area and an implantation actual surface exposed through a photoetching process; A second ion implantation structure of a second conductivity type located in the implantation target region, wherein the second ion implantation structure is formed by performing an ion implantation process to the implantation target surface, and A first conductive structure and a second conductive structure connected to an end of the implantation target region; the resistance value corresponding to the implantation target region can be obtained through the first conductive structure and the second conductive structure, and the offset between the second ion implantation structure and the implantation target region can be obtained through the resistance value, wherein the offset is the overlay accuracy.
2. The overlay accuracy monitoring structure of claim 1, wherein the implant target region extends along a first direction; The first ion implantation structure is provided with a plurality of implantation target areas, the implantation target areas are arranged along a second direction, and the second direction is perpendicular to the first direction; the overlay accuracy monitoring structure comprises a plurality of second ion implantation structures, and one second ion implantation structure is correspondingly positioned in one implantation target area; the overlay accuracy monitoring structure further comprises a plurality of connecting structures, wherein the connecting structures are connected with the end parts of two adjacent injection target areas to form a series structure; Wherein the first conductive structure is connected with an end of the implantation target region located at the head of the series structure, and the second conductive structure is connected with an end of the implantation target region located at the tail of the series structure.
3. The overlay accuracy monitor structure according to claim 1 or 2, further comprising a plurality of isolation structures located in the first ion implantation structure, adjacent two of the isolation structures defining one of the implantation target regions.
4. The overlay accuracy monitoring structure of claim 3, further comprising a plurality of dummy gate structures located on the first ion implantation structure, a space between two adjacent dummy gate structures exposing a surface of the implantation target region and a portion of the isolation structure.
5. An overlay accuracy monitoring method, characterized in that an overlay accuracy monitoring structure according to any one of claims 1 to 4 is adopted, and the overlay accuracy monitoring method comprises: acquiring a first square resistance value of the first ion implantation structure; Acquiring a second square resistance value of the second ion implantation structure; detecting and obtaining the resistance value corresponding to the implantation target area, and And calculating the offset between the second ion implantation structure and the implantation target region according to the first square resistance value, the second square resistance value and the resistance value corresponding to the implantation target region, wherein the offset is the overlay accuracy.
6. A semiconductor structure is characterized by comprising an LDMOS device and the overlay accuracy monitoring structure according to any one of claims 1-4, wherein the LDMOS device and the overlay accuracy monitoring structure are formed on the same semiconductor substrate, and a photomask forming a body region in the LDMOS device and a photomask exposing an implanted actual surface in the overlay accuracy monitoring structure are the same photomask.
7. A method of manufacturing a semiconductor structure, the method comprising: providing a semiconductor substrate; Performing a first ion implantation process on the semiconductor substrate to form a drift region and a first ion implantation structure in the semiconductor substrate, wherein the drift region and the first ion implantation structure are of a first conductivity type; defining a strip-shaped implantation target area in the first ion implantation structure; Forming a patterned photoresist layer on the semiconductor substrate by utilizing a body region photomask, wherein the patterned photoresist layer is provided with a first opening window and a second opening window, the first opening window exposes part of the surface of the drift region, and the second opening window exposes an implantation actual surface of the first ion implantation structure; Performing a second ion implantation process on the semiconductor substrate through the first and second windows to form a first body region in the drift region and a second ion implantation structure in the implantation target region, the first and second ion implantation structures being of a second conductivity type, and And forming a first conductive structure and a second conductive structure, wherein the first conductive structure and the second conductive structure are respectively connected with the end part of the implantation target region.
8. The method of manufacturing a semiconductor structure according to claim 7, wherein after performing a second ion implantation process on the semiconductor substrate through the first window and the second window, before forming the first conductive structure and the second conductive structure, the method of manufacturing a semiconductor structure further comprises: performing a trimming process on the patterned photoresist layer to enlarge the first opening and expose a portion of the surface of the drift region on the first body side, and And performing a third ion implantation process on the semiconductor substrate through the enlarged first window to form a second body region on the first body region side.
9. The method of manufacturing a semiconductor structure according to claim 7, wherein forming a first conductive structure and a second conductive structure, the first conductive structure and the second conductive structure being connected to ends of the implantation target region, respectively, comprises: Forming a dielectric layer covering the semiconductor substrate to expose the end of the implantation target region, and The first conductive structure and the second conductive structure are formed in the dielectric layer.
10. The method of manufacturing a semiconductor structure of claim 7, wherein defining a stripe-shaped implant target region in the first ion implantation structure comprises: A plurality of isolation structures are formed in the first ion implantation structure, and two adjacent isolation structures define one implantation target region.
11. The method of manufacturing a semiconductor structure of claim 7, wherein prior to forming a patterned photoresist layer on the semiconductor substrate using a body mask, the method further comprises: And forming a plurality of imitation gate structures and at least one pair of gate structures on the semiconductor substrate, wherein the space between two adjacent imitation gate structures exposes the surface of the implantation target region, and the space between the pair of gate structures exposes part of the surface of the drift region.

Description

Overlay accuracy monitoring structure, monitoring method, semiconductor structure and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to an overlay accuracy monitoring structure, an overlay accuracy monitoring method, a semiconductor structure, and a manufacturing method thereof. Background An LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor) device is one of core devices of a BCD (Bipolar-CMOS-DMOS) process platform product, can be compatible with BJT (Bipolar Junction Transistor ) devices and CMOS (Complementary Metal-Oxide-Semiconductor) device manufacturing processes, has high-voltage and high-current driving capability characteristics, and has extremely low power consumption in a switching mode. The LDMOS device is composed of hundreds of LDMOS cells of a single structure, the area of which is determined by the driving capability required by the chip. Taking a power management chip as an example, the LDMOS device occupies more than half of the chip area. Therefore, the performance of the LDMOS device directly determines the driving capability and area of the whole chip. In the prior LDMOS device body region forming process, a window is formed through a body region photomask, then a high-energy deep region is injected into a semiconductor substrate through the window, and then a low-energy shallow region is injected into the semiconductor substrate after the window is enlarged through a photoresist trimming (PR TRIMMING) process to form a body region. The threshold Voltage (VTH) and drain leakage current (IDL) of an LDMOS device are determined primarily by the channel formed by double diffusion of low energy implanted ions during thermal annealing, which implantation may be reflected by the linear region threshold Voltage (VTL) parameters. High energy ion implantation before photoresist trimming can affect body resistance, which may cause a series of problems such as latch up (latch up), increased power consumption, increased high voltage leakage, etc., but high energy ion implantation before photoresist trimming cannot pass WAT test (WAFER ACCEPTANCE TEST ) of the device. Disclosure of Invention The invention aims to provide an overlay accuracy monitoring structure, a monitoring method, a semiconductor structure and a manufacturing method thereof, which are used for solving the problem that overlay accuracy cannot be monitored in the prior art. In order to solve the technical problem, the present invention provides an overlay accuracy monitoring structure, which includes: The first ion implantation structure is of a first conductivity type, and is provided with a strip-shaped implantation target area and an implantation actual surface exposed through a photoetching process; A second ion implantation structure of a second conductivity type located in the implantation target region, wherein the second ion implantation structure is formed by performing an ion implantation process to the implantation target surface, and A first conductive structure and a second conductive structure connected to an end of the implantation target region; the resistance value corresponding to the implantation target region can be obtained through the first conductive structure and the second conductive structure, and the offset between the second ion implantation structure and the implantation target region can be obtained through the resistance value, wherein the offset is the overlay accuracy. Optionally, in the overlay accuracy monitoring structure, the implantation target region extends along a first direction; The first ion implantation structure is provided with a plurality of implantation target areas, the implantation target areas are arranged along a second direction, and the second direction is perpendicular to the first direction; the overlay accuracy monitoring structure comprises a plurality of second ion implantation structures, and one second ion implantation structure is correspondingly positioned in one implantation target area; the overlay accuracy monitoring structure further comprises a plurality of connecting structures, wherein the connecting structures are connected with the end parts of two adjacent injection target areas to form a series structure; Wherein the first conductive structure is connected with an end of the implantation target region located at the head of the series structure, and the second conductive structure is connected with an end of the implantation target region located at the tail of the series structure. Optionally, in the overlay accuracy monitoring structure, the overlay accuracy monitoring structure further includes a plurality of isolation structures, the isolation structures are located in the first ion implantation structure, and two adjacent isolation structures define one implantation target region. Optionally, in the overlay accuracy monitoring structure, the overlay accurac