CN-121978881-A - Undisturbed switching interface for simulation verification system, simulation verification system and simulation verification method

CN121978881ACN 121978881 ACN121978881 ACN 121978881ACN-121978881-A

Abstract

The invention relates to an undisturbed switching interface for a simulation verification system, the simulation verification system and a simulation verification method, comprising a logic calculation module, an instruction difference output module, a switching completion output module and an execution instruction output module; the logic calculation module performs logic calculation verification on the verification instruction and the matched instruction of the matched control system according to the undisturbed switching instruction and outputs a calculation verification result, monitors a switching state and generates a switching completion instruction, outputs an on/off execution instruction and/or an analog quantity instruction, the instruction difference output module outputs an instruction difference request synchronous signal according to the calculation verification result, the switching completion output module outputs a switching completion prompt signal, and the execution instruction output module outputs the on/off execution signal, the analog quantity instruction and the calculation verification result and the switching result to the monitoring unit. The invention can automatically complete debugging and verification after the simulation model is connected with the DCS, can rapidly complete undisturbed switching of various DCS control systems, and remarkably improves verification efficiency.

Inventors

WANG QIANXI
FENG QIANG
WANG XUEQI
ZHANG CHENGPO

Assignees

中广核(上海)仿真技术有限公司
中广核智能科技(深圳)有限责任公司

Dates

Publication Date: 20260505
Application Date: 20260107

Claims (10)

1. The undisturbed switching interface for the simulation verification system is characterized by comprising a logic calculation module, an instruction difference output module, a switching completion output module and an execution instruction output module; the system comprises a logic computing module, a signal triggering module, a matched control system, a command difference output module, a switching completion output module, a logic computing module, a process model and a monitoring unit, wherein the logic computing module is respectively connected with the verified system, the signal triggering module and the matched control system; The logic calculation module is used for carrying out logic calculation and verification on the verification instruction output by the verified system and the matched instruction output by the matched control system according to the undisturbed switching instruction output by the signal triggering module, and outputting a corresponding calculation verification result according to the logic calculation and verification; the instruction difference output module is used for outputting an instruction difference request synchronous signal according to the calculation verification result; The switching completion output module is used for outputting a switching completion prompt signal according to the switching completion instruction; The execution instruction output module is used for outputting the analog quantity instruction to the process model according to the on/off execution signal and the analog quantity instruction output by the execution instruction output module, and the execution instruction output module also outputs the calculation verification result and the switching result to the monitoring unit.
2. The undisturbed switching interface for a simulated verification system of claim 1, wherein said logic computation module comprises a first OR gate, a second OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a first equivalue comparator, a second equivalue comparator, a third OR gate, a buffer, an absolute value circuit, a less than circuit, a clock circuit, and a fourth OR gate; The input end of the first OR gate is connected with the undisturbed switching instruction, the output end of the first OR gate is respectively connected with the first input end of the second AND gate, the first input end of the fourth AND gate and the first input end of the sixth AND gate, the input end of the second OR gate is connected with a simulation mode signal, the output end of the second OR gate is connected with the input end of the switching completion output module, the first input end of the first equivalue comparator is connected with a matched opening instruction in the matched instruction, the second input end of the first equivalue comparator is connected with a verified opening instruction in the verified instruction, the output end of the first equivalue comparator is respectively connected with the first input end of the first AND gate and the second input end of the second AND gate, the first input end of the second equivalue comparator is connected with a matched closing instruction in the matched instruction, the second input end of the second equivalue comparator is connected with a verified closing instruction in the verified instruction, and the output end of the second equivalue comparator is respectively connected with the first input end of the second AND gate; The output end of the second AND gate is connected with the first input end of the third AND gate, the second input end of the third AND gate is connected with the output end of the fourth AND gate, the output end of the third AND gate is connected with the first input end of the fifth AND gate, the output end of the fifth AND gate is connected with the second input end of the third OR gate, the first input end of the third OR gate is connected with a forced switching instruction, the output end of the third OR gate is connected with the switching completion output module, the second input end of the sixth AND gate is connected with the second output end of the less than circuit, the output end of the sixth AND gate is connected with the first input end of the clock circuit, the first input end of the buffer is connected with a matched SP instruction in the matched instruction, the second input end of the buffer is connected with the verified SP instruction in the verified instruction, the output end of the buffer is connected with the first input end of the less than circuit through the absolute value taking circuit, and the first output end of the less than circuit is connected with the second input instruction of the less than circuit; The second input end of the clock circuit is connected with an access attempt time signal, the output end of the clock circuit is connected with the second input end of the fourth OR gate, the first input end of the fourth OR gate is connected with the switching completion output module, and the output end of the fourth OR gate is connected with the execution instruction output module.
3. The undisturbed switching interface for a simulation verification system of claim 2, wherein said instruction difference output module comprises a seventh AND gate, an NOT gate, and an instruction difference processing circuit; the first input end of the seventh AND gate is connected with the output end of the first AND gate, the second input end of the seventh AND gate is connected with the first output end of the less than taking circuit, the output end of the seventh AND gate is connected with the input end of the instruction difference processing circuit through the NOT gate, and the output end of the instruction difference processing circuit outputs the instruction difference request synchronous signal.
4. The undisturbed switching interface for a simulation verification system of claim 2, wherein said switching completion output module comprises a delay circuit and a switching completion instruction output circuit; The first input end of the delay circuit is connected with the output end of the third OR gate, the second input end of the delay circuit is connected with the output end of the second OR gate, the output end of the delay circuit outputs the switching completion instruction through the switching completion instruction output circuit, and the output end of the delay circuit is also connected to the execution instruction output module.
5. The undisturbed switching interface for a simulation verification system of claim 1, wherein said execution instruction output module comprises a first selector, an on instruction output module, a second selector, an off instruction output module, a third selector, an analog output module, and a buffer cancellation module; a first input end of the first selector is connected with a matched opening instruction in the matched instructions, a second input end of the first selector is connected with a verification opening instruction in the verification instructions, a third input end of the first selector is connected with the logic calculation module, an output end of the first selector is connected with an input end of the opening instruction output module, and an output end of the opening instruction output module outputs an opening execution signal in the opening/closing execution signals; The first input end of the second selector is connected with a matched closing instruction in the matched instructions, the second input end of the second selector is connected with a verification closing instruction in the verification instructions, the third input end of the second selector is connected with the logic calculation module, the output end of the third selector is connected with the input end of the closing instruction output module, and the output end of the closing instruction output module outputs a closing execution signal in the on/off execution signals; The input end of the buffering cancellation module is connected with the logic calculation module, the output end of the buffering cancellation module is connected with the third input end of the third selector, the first input end of the third selector is connected with the matched SP instruction in the matched instructions, the second input ends of all the third selectors are connected with the verification SP instruction in the verification instructions, the third input end of the third selector is connected with the logic calculation module and the buffering setting time, the output end of the third selector is connected with the input end of the analog output module, and the output end of the analog output module outputs the analog instructions.
6. The undisturbed switching interface for a simulated verification system as claimed in any one of claims 1-5, wherein said undisturbed switching interface is a device-targeted one-to-one switching interface.
7. A simulation verification system is characterized by comprising the undisturbed switching interface for the simulation verification system, a matched control system, a signal trigger module and a monitoring unit according to any one of claims 1-6; the signal triggering module is used for outputting undisturbed switching instructions according to triggering operations of users; the matched control system generates a matched instruction; The undisturbed switching interface is respectively connected with the signal triggering module, the matched control system and the process model and is used for rapidly completing preparation work before verification of a verified system; The monitoring unit is used for monitoring the switching process and the switching result in real time and displaying the switching result in a visual mode.
8. A simulation verification method applied to the simulation verification system as claimed in claim 7, comprising the steps of: receiving an undisturbed switching instruction; Acquiring a matching instruction and a verification instruction according to the undisturbed switching instruction; performing logic calculation according to the matching instruction and the verification instruction to judge whether the matching instruction and the verification instruction are matched; If the switching is matched, outputting an on/off execution instruction and/or an analog quantity instruction to the process model, and outputting a switching completion instruction after switching is completed; If not, outputting a switching interruption difference prompt signal.
9. The simulation verification method of claim 8, wherein the method further comprises: outputting an adjusting instruction to the verified system for adjustment according to the switching interruption difference prompt signal; judging whether the adjustment is completed within a specified time; If the adjustment is completed, re-executing the switching verification logic calculation; if the adjustment is not completed, outputting a switching failure prompt signal.
10. The simulation verification method of claim 8, wherein the method further comprises: and carrying out real-time monitoring and visual display on the switching process and the switching result.

Description

Undisturbed switching interface for simulation verification system, simulation verification system and simulation verification method Technical Field The invention relates to the technical field of nuclear power simulation, in particular to a undisturbed switching interface for a simulation verification system, a simulation verification system and a simulation verification method. Background In the simulation verification system, the interfaces of the conventional DCS and the simulation model are simply connected in a point-to-point manner by manpower, so that the point-to-point basis is completed, after the point-to-point work of the interfaces is completed, the point condition and the initial condition parameters after the DCS and the model are manually debugged are required to be checked, the verification working condition is stabilized, and the verification execution is convenient. However, in this manner, after the simulation model is connected with the DCS, debugging and verification cannot be automatically completed, undisturbed switching of various DCS control systems cannot be completed, and the debugging position or the debugging requirement of the control signal cannot be automatically determined. Disclosure of Invention The invention aims to solve the technical problem of the prior art and provides a undisturbed switching interface for a simulation verification system, the simulation verification system and a simulation verification method. The invention solves the technical problems by adopting the technical proposal that a undisturbed switching interface for a simulation verification system is constructed, which comprises a logic calculation module, an instruction difference output module, a switching completion output module and an execution instruction output module; the system comprises a logic computing module, a signal triggering module, a matched control system, a command difference output module, a switching completion output module, a logic computing module, a process model and a monitoring unit, wherein the logic computing module is respectively connected with the verified system, the signal triggering module and the matched control system; The logic calculation module is used for carrying out logic calculation and verification on the verification instruction output by the verified system and the matched instruction output by the matched control system according to the undisturbed switching instruction output by the signal triggering module, and outputting a corresponding calculation verification result according to the logic calculation and verification; the instruction difference output module is used for outputting an instruction difference request synchronous signal according to the calculation verification result; The switching completion output module is used for outputting a switching completion prompt signal according to the switching completion instruction; The execution instruction output module is used for outputting the analog quantity instruction to the process model according to the on/off execution signal and the analog quantity instruction output by the execution instruction output module, and the execution instruction output module also outputs the calculation verification result and the switching result to the monitoring unit. In the undisturbed switching interface for the simulation verification system, the logic calculation module comprises a first OR gate, a second OR gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a first equal value comparator, a second equal value comparator, a third OR gate, a buffer, an absolute value taking circuit, a less than circuit, a clock circuit and a fourth OR gate; The input end of the first OR gate is connected with the undisturbed switching instruction, the output end of the first OR gate is respectively connected with the first input end of the second AND gate, the first input end of the fourth AND gate and the first input end of the sixth AND gate, the input end of the second OR gate is connected with a simulation mode signal, the output end of the second OR gate is connected with the input end of the switching completion output module, the first input end of the first equivalue comparator is connected with a matched opening instruction in the matched instruction, the second input end of the first equivalue comparator is connected with a verified opening instruction in the verified instruction, the output end of the first equivalue comparator is respectively connected with the first input end of the first AND gate and the second input end of the second AND gate, the first input end of the second equivalue comparator is connected with a matched closing instruction in the matched instruction, the second input end of the second equivalue comparator is connected with a verified closing instruction in the verified instruction, and the output end of the second equival