CN-121979013-A - Wafer reliability control method

CN121979013ACN 121979013 ACN121979013 ACN 121979013ACN-121979013-A

Abstract

The application relates to the technical field of chips, and provides a wafer reliability control method which comprises the steps of making a test plan, determining items, parameters and test conditions which need to be tested for wafer reliability control, obtaining a target chip with the same process as a wafer, determining a test target structure of each item and a layer where the test target structure is located, removing the target chip layer by layer to obtain a target structure of the target chip, positioning the target structure of the target structure which needs to be tested on the target layer and a target position of the target structure on the target layer, setting the test conditions according to the determined target position, collecting characteristic parameters of the target structure by using a nano probe imaging analysis system, obtaining reliability control performance indexes of the target chip according to the characteristic parameters of the target structure, and establishing a reliability control scheme of a new wafer process according to the reliability performance indexes of the target chip. The method provided by the application can quickly establish a wafer reliability control scheme of a new process.

Inventors

ZHANG QIHUA
ZHANG JIE
JIAN WEITING
XU HONGWEI
Lv Youlong
Request for anonymity

Assignees

洪启集成电路(珠海)有限公司

Dates

Publication Date: 20260505
Application Date: 20251205

Claims (10)

1. The wafer reliability control method is characterized by comprising the following steps: s110, making a test plan, and determining items to be tested for wafer reliability control, parameters to be acquired for each item and test conditions; s120, acquiring a target chip in the same process as the wafer, acquiring a hierarchical structure of the target chip, controlling items to be tested according to the reliability, and determining a test target structure of each item and a hierarchy of the test target structure; S130, removing the target chip layer by layer from one side, sequentially obtaining each target layer of the target chip, positioning a target structure of the target layer to be tested and a target position of the target structure on the target layer every time one target layer is obtained; s140, setting testing conditions according to the determined target positions for each target layer, and collecting characteristic parameters of a target structure by using a nano probe imaging analysis system; S150, obtaining the reliability control performance index of the target chip according to the characteristic parameters of the target structure, and establishing a reliability control scheme of a new wafer manufacturing process according to the reliability performance index of the target chip.
2. The method of claim 1, wherein the step S120 is to obtain a target chip in the same process as the new wafer process, specifically, obtain a target package device in the same process as the new wafer process, and remove the package of the target package device to obtain the target chip of the target package device.
3. The method of claim 2, wherein in the step 120, at least two target packaging devices are obtained, one of the target packaging devices is selected as a first target packaging device, the packaging of the first target packaging device is removed, a first target chip of the first target packaging device is obtained, and a hierarchical structure of the first target chip is obtained; step 130 includes, removing the first target chip layer by layer from one side, sequentially obtaining each target layer of the first target chip, positioning a target structure of an item to be tested of the target layer, and a target position of the target structure on the target layer; step 140 includes selecting a second target packaging device as a second target packaging device, removing packaging of the second target packaging device to obtain a second target chip, removing the second target chip layer by layer, and collecting characteristic parameters of the target structure according to the target structure determined in step 130 and the target position of the target structure tested by using a nanoprobe imaging analysis system; The step S150 includes obtaining a reliability control performance index of the target chip according to the feature parameters of the target structure of the second target chip, and establishing a reliability control scheme of a new wafer manufacturing process according to the reliability performance index of the target chip.
4. The method of any one of claims 1 to 3, further comprising, after each target layer is obtained and a target structure of the target layer is determined, and a target location of the target structure, the step of performing circuit repair on the target structure using the FIB from the target location to isolate the target structure from the target location.
5. The method of claim 4, wherein in step S110, the item of reliability test is a constant temperature electromigration effect test, and the test conditions are a temperature condition and a current density condition; the step S140 specifically includes selecting, for each target layer, a metal wire with a length not less than a preset length, and testing the metal wire according to the following steps: S141, acquiring the width W and the length L of the metal wire; s142, setting temperature, adjusting current density under the set temperature condition, and measuring to obtain different current density data sets under the same temperature condition; S143, setting current density, adjusting temperature under the set current density condition, and measuring to obtain different temperature data sets under the same current density condition; In the step S150, the reliability of the constant temperature electromigration effect of the target chip is obtained according to the obtained data sets of different current densities under the same temperature condition and the obtained data sets of different temperatures under the same current density condition, and the reliability control scheme of the new wafer manufacturing process is established according to the reliability of the constant temperature electromigration effect of the target chip.
6. The method of claim 5, wherein at least three sets of data sets of different current densities under the same temperature condition are obtained in step S142, and wherein at least three sets of data sets of different temperatures under the same current density condition are obtained in step S143.
7. The method according to claim 6, wherein in the step S120, the hierarchical structure of the target chip is obtained by SEM, FIB or TEM.
8. An electronic device comprising a memory storing a computer executable program and a processor invoking the computer executable program in the memory to implement the wafer reliability control method of any of claims 1-7.
9. A storage medium, characterized in that the storage medium is a computer-readable storage medium, on which a computer-executable program is stored, which when executed by a processor, implements the wafer reliability control method according to any one of claims 1 to 7.
10. A program product comprising a computer executable program which, when run, performs the wafer reliability control method of any one of claims 1 to 7.

Description

Wafer reliability control method Technical Field The invention relates to the technical field of chip processing, in particular to a wafer reliability control method. Background As a wafer foundry, a reliability control scheme for a new process in a wafer factory needs to be established when a new process is developed. The traditional wafer reliability control scheme is established, the new wafer manufacturing process is determined, basic Testkey (test structure/unit device), TQV (Technology Qualification Vehicle, technical identification vehicle), PQV (Product Qualification Vehicle, product identification vehicle) and the like are designed, after a flow sheet runs out of a wafer, a wafer-level reliability test is carried out by a tester to obtain parameters of a reliability test item, the parameters are formulated according to the obtained test result, a large number of wafers in multiple batches are run out in the subsequent process, and the reliability control scheme aiming at the new manufacturing process is finally formed through multiple measurement and adjustment optimization. The method needs to wait for a wafer tester aiming at a new process, and can start formulation after a wafer is discharged, and then a more complete reliability control scheme can be finally formed after the wafer is regulated for many times. The whole process is long in time consumption and high in investment, which can influence the production of a new manufacturing process. On the other hand, in the process of formulating a reliability control scheme for a new process, the defect may be considered, so that one or more important projects are not measured, or the measured data is wrong, and the test machine needs to be redesigned to perform the test, so that the cost is high, the period is long, and the production of the new process is also influenced. Disclosure of Invention Based on the problems of the prior art, the embodiment of the application provides a wafer reliability control method which can help wafer manufacturers to develop a control scheme for a new process as soon as possible in the process of developing the new process, accelerate the production of the new process as soon as possible, and simultaneously provide a quick and low-cost scheme for the development of supplementary test of certain important data in the process of the new process. The embodiment of the application also provides a wafer reliability control method, which comprises the following steps: s110, making a test plan, and determining items to be tested for wafer reliability control, parameters to be acquired for each item and test conditions; s120, acquiring a target chip in the same process as the wafer, acquiring a hierarchical structure of the target chip, controlling items to be tested according to the reliability, and determining a test target structure of each item and a hierarchy of the test target structure; S130, removing the target chip layer by layer from one side, sequentially obtaining each target layer of the target chip, positioning a target structure of the target layer to be tested and a target position of the target structure on the target layer every time one target layer is obtained; s140, setting testing conditions according to the determined target positions for each target layer, and collecting characteristic parameters of a target structure by using a nano probe imaging analysis system; S150, obtaining the reliability control performance index of the target chip according to the characteristic parameters of the target structure, and establishing a reliability control scheme of a new wafer manufacturing process according to the reliability performance index of the target chip. The wafer reliability control method provided by the application is mainly used for testing and obtaining the reliability test parameters of the traditional wafer process through a testing machine, wherein the testing machine is required to design a special Testkey and a special test Pad (Pad) on the wafer, and then a nano-scale device on Testkey can be tested through a needle (Probe) point on a chuck (Probe Card) on the Pad. The needles on the tester chuck are usually thicker than 1um, so that the tester can only test the wafer through specially designed test pads (the test pads are usually larger than 20um x 20 um) on the wafer to obtain the reliability test parameters of the wafer. And a single chip cannot be tested to obtain the reliability test parameters. When developing a wafer process for a more advanced process, a wafer manufacturer who is a catch-up man in a domestic wafer foundry is always a mature process for an international leading wafer foundry. Because of the security management of these leading wafer manufacturers, the domestic manufacturers who are catch-up cannot directly obtain the process of their prior processes, cannot obtain samples of the complete wafer or the wafer with the complete wafer-level process reliability test struc